Patents by Inventor Kentaro Hyodo

Kentaro Hyodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuitry, DRAM circuitry
    Patent number: 11683927
    Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias. Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 20, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Ishigami, Kentaro Hyodo
  • Integrated Circuitry, DRAM Circuitry, Method Used in Forming Integrated Circuitry, and Method Used in Forming Memory Circuitry
    Publication number: 20210408007
    Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias. Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hitoshi Ishigami, Kentaro Hyodo
  • Method used in forming integrated circuitry, and method used in forming memory circuitry
    Patent number: 11152372
    Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Ishigami, Kentaro Hyodo
  • Integrated Circuitry, DRAM Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry
    Publication number: 20210265359
    Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hitoshi Ishigami, Kentaro Hyodo