Abstract: A computer-readable recording medium stores a matrix operation program for a computer. In a matrix operation in which an arithmetic circuit executes processing that combines at least two columns included in a matrix, obtains a product of each of rows of the combined columns, and calculates a sum of the product of each of the rows for all combinations of columns in the matrix, the program causes the computer to divide the matrix into blocks of a column group based on a data size of the column and storage capacity of a second storage to be accessed by the arithmetic circuit prior to accessing a first storage that stores information related to the matrix such that the column group to be combined is contained in the second storage, and to execute the calculation processing for each block of the divided column group.

Abstract: Provided is a non-transitory computer-readable recording medium storing a function generation program that causes a computer to execute a process, the process including referring to a storage unit that stores instruction information about an instruction to generate a first function that corresponds to the instruction and receives one or more arguments representing one or more operands of the instruction, generating first code inside the first function, where the first code calls a second function that returns machine language representing a process executed by the instruction for the one or more operands represented by the one or more arguments, and generating second code inside the first function, where the second code writes the machine language in a memory.

Abstract: A non-transitory computer-readable recording medium stores a program for causing a computer to execute a process, the process includes, in a search for combinations of conditions that allow extraction of sample data groups that have n or more attribute pairs whose correlation coefficients exceed a threshold value, when a number of combinations of the conditions is equal to or greater than a number capable of being parallelized, parallelizing processing for the combinations of the conditions per the number capable of being parallelized to calculate the correlation coefficients of respective attribute pairs for each of the combinations of the conditions in addition to a single instruction multiple data (SIMD) conversion process that uses predicate registers as many as the number capable of being parallelized, and searching for the combinations of conditions using the correlation coefficients of the respective attribute pairs for each of the combinations of the conditions.

Abstract: A recording medium stores a program for causing a computer to execute a process including: converting, in a first source code corresponding to a first-type processor, a first load command for a first mask register included in the first-type processor into a second load command for a second mask register included in a second-type processor; and converting, when a first SIMD command for performing an arithmetic operation using the first mask register exists after the first load command in the first source code and a state of a value of the first mask register does not coincide with a state of a value of the first mask register, the first SIMD command into a second SIMD command corresponding to the second-type processor and a change command for changing a state of a value of the second mask register to a state of a value of the second mask register.

Abstract: An instruction sequence generation program for a process including: inputting an instruction sequence for an assembler that processes predetermined operations, and generating the instruction sequence based on a number of SIMD registers, a number of registers to hold values dependent on input values, and a number of registers to hold values independent of input values.

Abstract: A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

Abstract: A recording medium stores a program for causing a computer to execute a process including: converting, in a first source code corresponding to a first-type processor, a first load command for a first mask register included in the first-type processor into a second load command for a second mask register included in a second-type processor; and converting, when a first SIMD command for performing an arithmetic operation using the first mask register exists after the first load command in the first source code and a state of a value of the first mask register does not coincide with a state of a value of the first mask register, the first SIMD command into a second SIMD command corresponding to the second-type processor and a change command for changing a state of a value of the second mask register to a state of a value of the second mask register.

Abstract: A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

Abstract: A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

Abstract: A processor includes a first register, a second register configured to store status information related to the first register, and a detection circuit configured to detect an exception in an instruction in which the first register is specified in an operand, based on the status information stored in the second register, wherein the status information has a first flag indicating whether the first register has been used as a write destination register before the execution of the instruction and a second flag indicating whether the first register has been used as a read source register before the execution of the instruction, and the detection circuit detects the exception when the first flag indicates that the first register has been used as the write destination register and the second flag indicates that the first register has not been used as the read source register.

Abstract: Provided is a non-transitory computer-readable recording medium storing a function generation program that causes a computer to execute a process, the process including referring to a storage unit that stores instruction information about an instruction to generate a first function that corresponds to the instruction and receives one or more arguments representing one or more operands of the instruction, generating first code inside the first function, where the first code calls a second function that returns machine language representing a process executed by the instruction for the one or more operands represented by the one or more arguments, and generating second code inside the first function, where the second code writes the machine language in a memory.

Abstract: This disclosure relates to a non-transitory computer-readable recording medium storing a class generation program that causes a computer to execute a process. The process includes a step S13 that acquires a first class, a second class, and a lexical token which are associated with each other by referring to a storage unit 53 that stores the first class, the second class, and the lexical token in association with each other, the first class representing a first format about a vector register vn, the second class representing a second format about the vector register vn and inheriting the first class; and a step S15 that generates any one of a first code 77 that generates an instance of the acquired second class and a second code 78 that overloads the acquired lexical token, inside the acquired first class depending on the acquired lexical token.

Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process. The process includes storing each of a plurality of generation instructions in a storage area for each of assembly instructions, the generation instructions instructing the generation of instruction sequences of a first instruction set, each instruction sequence of the first instruction set executing a processing equivalent to each assembly instruction of a second instruction set, identifying a first register that is not used by any of the assembly instructions corresponding to the plurality of generation instructions by referring to the storage area, determining a second register of the first instruction set corresponding to the first register as a temporary register in each of the instruction sequences, and generating the instruction sequence that uses the temporary register.

Abstract: A non-transitory computer-readable medium having stored therein a program for causing a computer to execute a process. The process includes storing a plurality of generation instructions in a storage area for each of a plurality of first assembly instructions, each generation instruction instructing the generation of a machine language of a second assembly instruction that executes processing equivalent to each first assembly instruction, and generating machine languages of a plurality of second assembly instructions so that the machine languages of the second assembly instructions having a dependency relationship do not appear adjacent to each other, according to the plurality of generation instructions in the storage area.

Abstract: A non-transitory computer-readable medium having stored therein a program for causing a computer to execute a process. The process includes storing a plurality of generation instructions in a storage area for each of a plurality of first assembly instructions, each generation instruction instructing the generation of a machine language of a second assembly instruction that executes processing equivalent to each first assembly instruction, and generating machine languages of a plurality of second assembly instructions so that the machine languages of the second assembly instructions having a dependency relationship do not appear adjacent to each other, according to the plurality of generation instructions in the storage area.

Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process. The process includes storing each of a plurality of generation instructions in a storage area for each of assembly instructions, the generation instructions instructing the generation of instruction sequences of a first instruction set, each instruction sequence of the first instruction set executing a processing equivalent to each assembly instruction of a second instruction set, identifying a first register that is not used by any of the assembly instructions corresponding to the plurality of generation instructions by referring to the storage area, determining a second register of the first instruction set corresponding to the first register as a temporary register in each of the instruction sequences, and generating the instruction sequence that uses the temporary register.

Abstract: A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

Abstract: A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

Abstract: A direct memory access (DMA) control device including: a basic-function setting register used to perform DMA operation; and a scatter-gather setting register in which a value indicating that a task is executed through setting of a directly defined value for data to be written to the basic-function setting register without reading the data from a memory through a bus is set.

Abstract: An integrated circuit system includes a first integrated circuit for which signal modes set to a plurality of first I/O ports in the active mode are maintained in the sleep mode and a second integrated circuit for which a plurality of second I/O ports are placed in a floating state in the sleep mode, wherein the first integrated circuit transmits a first notification signal that indicates an operation mode to the second integrated circuit, wherein the second integrated circuit transmits a second notification signal that indicates an operation mode to the first integrated circuit, and wherein the signal modes of the plurality of first I/O ports and the plurality of second I/O ports are set such as to suppress steady currents persistently flowing between the first I/O ports and the second I/O ports, and to suppress through currents flowing.