Patents by Inventor Kentaro Kitamura

Kentaro Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927857
    Abstract: A display device includes: an array substrate; a counter substrate; a liquid crystal layer between the array substrate and the counter substrate; and a light source disposed so as to emit light into a side surface of the array substrate or a side surface of the counter substrate. The array substrate includes: signal lines arranged in a first direction with spaces interposed between the signal lines; scan lines arranged in a second direction with spaces interposed therebetween; a switching element coupled to a corresponding one of the scan lines and a corresponding one of the signal lines; an organic insulating layer that covers at least the switching element; and a metal layer provided on the upper side of the organic insulating layer so as to overlap the organic insulating layer. A positional misalignment portion of each signal line does not overlap a positional misalignment portion of the metal layer.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: March 12, 2024
    Assignee: Japan Display Inc.
    Inventors: Yoshihide Ohue, Yuuji Oomori, Koji Kitamura, Kentaro Okuyama
  • Patent number: 5682175
    Abstract: A data driver for a matrix display device includes a shift register circuit for sequentially shifting a sampling start pulse in response to a clock signal to produce a plurality of sampling signals. A plurality of sample/hold circuits sample display data in response to a sampling signal supplied thereto. The driver also includes a switching circuit which transfers each of the sampling signals to an associated one of the sample/hold circuits in a sequential-sampling mode and the selected signals to the sample/hold circuits such that one of the selected sampling signals is supplied in common to at least two of the sample/hold circuits.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: October 28, 1997
    Assignee: NEC Corporation
    Inventor: Kentaro Kitamura