Patents by Inventor Kentaro Kuhara

Kentaro Kuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941011
    Abstract: A provision method provides plurality of pieces of advice pertaining to household appliances of a user on a tablet 103. A priority of each piece of advice is changed by determining whether an advice-specific standard for the user the reference that piece of advice is met by an auto-log or overall user information. The pieces of advice are displayed in accordance with determination results. The format of display according to determination results is a list of advice sorted by priority.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: March 26, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hiroshi Yoshitake, Hideo Umetani, Kentaro Nakai, Keigo Aso, Shunsuke Kuhara
  • Patent number: 6492692
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: December 10, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Patent number: 6468825
    Abstract: A method for producing a semiconductor temperature sensor comprises the steps of forming PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transistors are formed at the same time, and connecting the PNP bipolar transistors in a Darlington connection.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: October 22, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Kentaro Kuhara, Toru Shimizu, Yoshikazu Kojima
  • Patent number: 6046492
    Abstract: A semiconductor temperature sensor comprises independent current sources and bipolar transistors connected to form a Darlington circuit. The bipolar transistors have electrodes each connected to one of the current sources. An output voltage of the semiconductor temperature sensor is adjusted by trimming a current value of at least one of the current sources.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: April 4, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Kentaro Kuhara, Toru Shimizu, Yoshikazu Kojima
  • Patent number: 6022792
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 8, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Patent number: 5483096
    Abstract: A photo sensor comprises a semiconductor substrate, a bipolar photo transistor having an emitter region, a base region and a collector region which is formed in the surface region of the semiconductor substrate, a silicon dioxide formed on the bipolar phototransistor, and a film having a smaller diffusion coefficient of hydrogen than the silicon dioxide formed all over the silicon dioxide.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: January 9, 1996
    Assignee: Seiko Instruments Inc.
    Inventor: Kentaro Kuhara