Patents by Inventor Kentaro Kumazawa

Kentaro Kumazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110061913
    Abstract: A method of manufacturing a mounting structure includes: an insulating resin arranging step of forming, on a circuit board, two kinds of insulating resin including first insulating resin cured at first curing temperature and second insulating resin cured at second curing temperature higher than the first curing temperature; a mounting step of aligning the bumps formed on an electronic component such that the bumps are opposed to counter electrodes of the circuit board; and a full-scale pressing step of performing, after the mounting step, full-scale pressing to join the electronic component and the circuit board. The insulating resin is heated to reach the first curing temperature before the full-scale pressing, and the insulating resin is heated to reach the second temperature during the full-scale pressing after the curing of the first insulating resin.
    Type: Application
    Filed: March 23, 2009
    Publication date: March 17, 2011
    Applicant: Panasonic Corporation
    Inventors: Takayuki Higuchi, Yoshihiro Tomura, Kazuhiro Nobori, Kentaro Kumazawa
  • Publication number: 20110042808
    Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.
    Type: Application
    Filed: April 14, 2009
    Publication date: February 24, 2011
    Inventors: Kentaro Kumazawa, Yoshihiro Tomura
  • Publication number: 20110020983
    Abstract: A flip-chip mounting apparatus has a shield film (18) on the side of a pressurizing film (10b) of a tool protection sheet (10). When a semiconductor chip (1) is heated and pressurized via the tool protection sheet (10), the pressurizing film (10b) is released from a mold by a sheet fixing jig (9), and is expanded by a pressurizing/heating tool (11) to abut against an insulating resin film (5) protruding from the periphery of the semiconductor chip (1) and cure the insulating resin film (5) with an external pressure being applied.
    Type: Application
    Filed: March 30, 2009
    Publication date: January 27, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshihiro Tomura, Kentaro Kumazawa, Takayuki Higuchi, Koujiro Nakamura
  • Publication number: 20100265683
    Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion (or a protruding portion 22) is formed in the surfaces of the circuit board 2.
    Type: Application
    Filed: April 21, 2009
    Publication date: October 21, 2010
    Applicant: Panasonic Corporation
    Inventors: Teppei IWASE, Kazuhiro NOBORI, Yoshihiro TOMURA, Koujiro NAKAMURA, Kentaro Kumazawa
  • Publication number: 20100181667
    Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding use resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding use resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. In the semiconductor chip mounted structure formed in this way, entire side faces at the corner portions of the semiconductor chip are covered with the seal-bonding use resin.
    Type: Application
    Filed: June 26, 2008
    Publication date: July 22, 2010
    Inventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
  • Publication number: 20100167597
    Abstract: The electrode junction structure includes: a glass substrate; a plurality of flexible substrates, in a planar view, arranged to cross over an edge of the glass substrate and arranged to have a space from each other along the edge; an adhesive for joining the glass substrate and each flexible substrate; and a sealing resin for covering junction portions between the glass substrate and each flexible substrate, wherein an edge of the sealing resin is formed so that the edge of the sealing resin has, in the planar view, a consecutive waveform portion in which a convex portion and a concave portion alternate with an imaginary line as a center axis, the imaginary line being parallel to the edge of the glass substrate and locating outer than the edge of the glass substrate, and wherein the convex portions are formed to be located on the flexible substrates.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Inventors: Kentaro KUMAZAWA, Masahiro ONO, Yoshihiro TOMURA
  • Publication number: 20100032832
    Abstract: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and then covering the surfaces of the cores 15 with a conductive electrode 16. When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.
    Type: Application
    Filed: May 9, 2008
    Publication date: February 11, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa, Teppei Iwase
  • Publication number: 20090321926
    Abstract: A mounting structure of the present invention includes a semiconductor element 101, a circuit board 301 having electrodes 302 opposed to electrodes 102 of the semiconductor element 101, and conductive two-layer bumps 213. Second bumps 210 joined to the electrodes 302 of the circuit board 301 are formed larger than first bumps 209 joined to the electrodes 102 of the semiconductor element 101. The axis of the first bump 209 and the axis of the second bump 210 are not aligned with each other.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 31, 2009
    Applicant: Panasonic Corporation
    Inventors: Kojiro Nakamura, Yoshihiro Tomura, Kentaro Kumazawa
  • Publication number: 20090278265
    Abstract: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire (5), the edge, in the vicinity of which the wire (5) passes, of the outer perimeter edge portions of the component (2) is formed to be a chamfered oblique surface (31), and the wire (5) is provided to extend to the board (1) along the oblique surface (31). By this means, the overall height of the electronic component can be kept low.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 12, 2009
    Applicant: Panasonic Corporation
    Inventors: Makoto Imanishi, Yoshihiro Tomura, Kentaro Kumazawa
  • Publication number: 20090267214
    Abstract: The electronic circuit device of the present invention includes at least one semiconductor element, a plurality of external connection terminals, a connecting conductor for electrically connecting semiconductor element and external connection terminals, and an insulating resin for covering the semiconductor element and supporting the connecting conductor integrally, in which the semiconductor element is buried in the insulating resin, and the terminal surface of the external connection terminals is exposed from the insulating resin.
    Type: Application
    Filed: October 19, 2006
    Publication date: October 29, 2009
    Inventors: Kentaro Kumazawa, Shigeru Kondou, Hidenobu Nishikawa
  • Publication number: 20080150133
    Abstract: A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads (2a) provided on a substrate upper surface (1a); a plurality of lower side pads (2b) provided on a substrate lower surface (1b) corresponding to the upper side pads (2a) across the substrate (1), respectively; a first semiconductor chip (4) having first bumps (8a) joined to the upper side pads (2a), respectively; and a second semiconductor chip (5) having second bumps (8b) joined to the lower side pads (2b), respectively.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 26, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kojiro Nakamura, Hidenobu Nishikawa, Kentaro Kumazawa