Abstract: An object is to provide a compound that can be a novel curing agent. The compound suppresses volatilization of the curing agent that can lead to a decrease in function of a prepreg, contamination of equipment for producing the prepreg, and in addition a decrease in production yield of the prepreg, and further contributes to improving dielectric properties. As a solution, a tris(allyl ether) compound represented by general formula (1) below is provided.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Abstract: A semiconductor device includes a first lead, a second lead spaced apart from the first lead in a first direction, a first semiconductor element on the first lead, a second semiconductor element on the second lead, and a sealing resin covering the first lead, the second lead, the first semiconductor element and the second semiconductor element. The first and second semiconductor elements respectively have first and second element side surfaces facing with each other in the first direction. The sealing resin has a first-direction middle plane equidistant from the first and the second element side surfaces in the first direction. The first lead includes a first main part, and the second lead includes a second main part. The first and the second main parts are spaced apart from each other with reference to the first-direction middle plane.

Abstract: A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: A semiconductor device includes a semiconductor chip having a main surface, a first conductivity type drift layer formed in a surface layer portion of the main surface, a trench gate structure formed in the main surface such as to be in contact with the drift layer, a second conductivity type channel region formed in the drift layer such as to cover a side wall of the trench gate structure, and first and second source/drain regions formed at intervals in a region along the side wall of the trench gate structure in the drift layer such as to oppose each other across the channel region.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface, a trench gate structure that includes a trench formed in the main surface and having a first sidewall at one side, a second sidewall at the other side and a bottom wall in a cross-sectional view, an insulation layer formed on an inner wall of the trench, and a gate electrode embedded in the trench with the insulation layer between the trench and the gate electrode and having an upper end portion positioned at a bottom-wall side with respect to the main surface, a plurality of first-conductivity-type drift regions that are respectively formed in a region at the first sidewall side of the trench and in a region at the second sidewall side of the trench such as to face each other with the trench interposed therebetween in a surface layer portion of the main surface and that are positioned in a region at the main surface side with respect to the bottom wall, and a plurality of first-conductivity-type source/drain regions that are forme

Abstract: A semiconductor device includes a first lead, a semiconductor element, a sealing resin, a first plating layer, and a second plating layer. The first lead has a first obverse surface and a first reverse surface facing opposite from each other in a thickness direction and a first recess recessed from the first reverse surface toward the first obverse surface. The semiconductor element is mounted on the first obverse surface. The sealing resin covers the semiconductor element. The first plating layer is formed in contact with the first obverse surface and the first reverse surface. The first recess is exposed from the sealing resin. The first plating layer includes a first portion covering the first reverse surface. The second plating layer is formed in contact with the first recess and the first portion.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame, mounting a semiconductor element on an obverse face of the lead frame, forming a sealing resin covering the semiconductor element, forming a groove on a reverse face of the lead frame, and removing a portion of the lead frame and a portion of the sealing resin along a disposal region that is narrower than the groove and entirely overlaps with the groove. The preparing of the lead frame includes forming at least one recess located in the disposal region and having an end that is open in the thickness direction. The forming of the groove includes exposing the recess on a side of the reverse face of the lead frame. The removing is performed with reference to the recess.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame, mounting a semiconductor element on an obverse face of the lead frame, forming a sealing resin covering the semiconductor element, forming a groove on a reverse face of the lead frame, and removing a portion of the lead frame and a portion of the sealing resin along a disposal region that is narrower than the groove and entirely overlaps with the groove. The preparing of the lead frame includes forming at least one recess located in the disposal region and having an end that is open in the thickness direction. The forming of the groove includes exposing the recess on a side of the reverse face of the lead frame. The removing is performed with reference to the recess.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall insulating film, including a side wall insulating film, formed along side walls of the diode trench, and a bottom wall insulating film, formed along a bottom wall of the diode trench and having a thickness greater than a thickness of the side wall insulating film, and a bidirectional Zener diode, formed on the bottom wall insulating film inside the diode trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions.