Patents by Inventor Kentaro Ooishi
Kentaro Ooishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9614055Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: GrantFiled: February 18, 2015Date of Patent: April 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20150179763Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: ApplicationFiled: February 18, 2015Publication date: June 25, 2015Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
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Patent number: 8987810Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: GrantFiled: January 31, 2014Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20140145259Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
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Patent number: 8704291Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: GrantFiled: January 11, 2013Date of Patent: April 22, 2014Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 8378413Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: February 22, 2011Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20120289013Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.Type: ApplicationFiled: July 26, 2012Publication date: November 15, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
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Publication number: 20110140198Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS, CO., LTD.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7910985Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: April 14, 2010Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20100193863Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: April 14, 2010Publication date: August 5, 2010Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS, CO., LTD.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20080233696Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: February 22, 2008Publication date: September 25, 2008Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7358141Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: July 11, 2006Date of Patent: April 15, 2008Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7189621Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: GrantFiled: November 12, 2004Date of Patent: March 13, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20060252192Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: July 11, 2006Publication date: November 9, 2006Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7098506Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: January 31, 2005Date of Patent: August 29, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20050127437Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: January 31, 2005Publication date: June 16, 2005Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20050082608Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: ApplicationFiled: November 12, 2004Publication date: April 21, 2005Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 6861703Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: September 9, 2003Date of Patent: March 1, 2005Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 6818949Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: GrantFiled: January 5, 2004Date of Patent: November 16, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20040140503Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: ApplicationFiled: January 5, 2004Publication date: July 22, 2004Applicant: Hitachi, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi