Patents by Inventor Kentaro Shimayama

Kentaro Shimayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130122706
    Abstract: According to one embodiment, a method of manufacturing of a semiconductor device is provided. In the method, a front surface of a semiconductor substrate and a front surface of a support substrate are bonded to each other by an adhesive. A part of a circumferential part of the support substrate is subjected to water-repellent treatment to thereby form a water-repellent area on the part of the circumferential part in such a manner that the water-repellent area and an end face of the adhesive are in contact with each other. The semiconductor substrate is removed from a rear surface side by wet etching.
    Type: Application
    Filed: March 23, 2012
    Publication date: May 16, 2013
    Inventors: Hisashi OKUCHI, Hidekazu Hayashi, Kentaro Shimayama, Hiroshi Tomita
  • Patent number: 7985683
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Publication number: 20100240219
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Application
    Filed: May 26, 2010
    Publication date: September 23, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Patent number: 7749909
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Publication number: 20100075504
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Application
    Filed: October 6, 2009
    Publication date: March 25, 2010
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Publication number: 20070181892
    Abstract: A spacer structure is provided between a first substrate formed with a phosphor screen and a second substrate provided with a plurality of electron emission sources. A supporting substrate of the spacer structure has a first surface opposed to the first substrate, a second surface opposed to the second substrate, and a plurality of electron beam apertures opposed to the electron emission sources. A plurality of spacers are set up on the second surface. The supporting substrate has a plurality of height reducing portions which are individually in contact with the spacers and elastically deformable in the height direction of the spacers. Each of the height reducing portions has a recess formed in the first surface so as to face the spacer and a plurality of grooves formed on the second surface and situated around the spacer.
    Type: Application
    Filed: March 2, 2007
    Publication date: August 9, 2007
    Inventors: Sachiko HIRAHARA, Satoko Oyaizu, Satoshi Ishikawa, Kentaro Shimayama
  • Publication number: 20070103053
    Abstract: Spacers and a grid unit are provided between a first substrate having a phosphor screen formed thereon and a second substrate provided with a plurality of electron emission sources. The grid unit includes a plate-shaped grid which has a plurality of electron beam apertures opposed to the electron emission sources, individually, and is located opposite the second substrate and to which a predetermined voltage is applied, and a first dielectric layer which covers an outer surface of the grid. The grid unit includes a conductive layer, which is provided between the first dielectric layer and the second substrate and connected to a ground potential, and a second dielectric layer formed covering the conductive layer and situated between the conductive layer and the second substrate.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 10, 2007
    Inventors: Nobuyuki AOYAMA, Sachiko HIRAHARA, Satoshi ISHIKAWA, Satoko OYAIZU, Kentaro SHIMAYAMA, Ken TAKAHASHI