Abstract: In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.

Abstract: In the case where a target device stores: m keys {Ka1, . . . , Kam} (m is a natural number) in a manner that the Kai (i is a natural number satisfying 1?i?m) is encrypted with the Ka (i?1); and n keys {Kb1, . . . , Kbn} (n is a natural number) in a manner that the Kbj (j is a natural number satisfying 1?j?n) is encrypted with the Kb (j?1), a confidential information processing unit is caused to perform a processing of re-encrypting the encrypted key Enc (Kai, Ka (i?1)), which has been encrypted with the Ka (i?1), by using the Kb (j?1) and outputting as an encrypted key Enc (Kai, Kb (j?1)).

Abstract: In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.

Abstract: In the case where a target device stores: m keys {Ka1, . . . , Kam} (m is a natural number) in a manner that the Kai (i is a natural number satisfying 1?i?m) is encrypted with the Ka (i?1); and n keys {Kb1, . . . , Kbn} (n is a natural number) in a manner that the Kbj (j is a natural number satisfying 1?j?n) is encrypted with the Kb (j?1), a confidential information processing unit is caused to perform a processing of re-encrypting the encrypted key Enc (Kai, Ka (i?1)), which has been encrypted with the Ka (i?1), by using the Kb (j?1) and outputting as an encrypted key Enc (Kai, Kb (j?1)).

Abstract: A domain key is used to perform chaining decryption with respect to encrypted content key information (ST203-1), and first data is extracted (ST203-2). The extracted first data is compared with partial-check data (ST203-4). The first data as it is encrypted is extracted from the m pieces of encrypted content key information (ST203-6), and a predetermined operation is executed with respect to concatenated data including m extracted check values to generate second data (ST203-8). The second data is compared with whole-check data included in domain key information (ST203-11). If the first data matches the partial-check data (ST203-5) and the second data matches the whole-check data (ST203-12), it is determined that there is not tampering.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: A Control Data Flow Graph (CDFG) which is an intermediate representation obtained by analyzing a behavioral-level circuit description of hardware, is subjected to a process of changing a shape of the CDFG by adding an operation before or after scheduling, so as to conceal design information. A CDFG to which a hardware resource has been allocated may be subjected to a process of changing the allocation of the hardware resource.

Abstract: A communication card comprised of: an interface unit which communicates with the host; a first communication unit which communicates with an external device other than the host; an encryption unit which performs encryption processing onto data transferred between the host device and the external device via the interface unit and the first communication unit; a storage unit which stores: list information indicating a list of identifiers of unauthorized communication cards; and communication key information used for encryption; and a control unit which performs authentication processing, and only when the authentication processing has been completed normally, allows the host to control the first communication unit, causes said encryption unit to encrypt the data by using the communication key information after the authentication processing, and transfers the encrypted data to the host via the interface unit, in which the authentication processing includes processing of revoking an unauthorized communication car

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: To provide a device unique key for establishing a system for protecting a device unique ID including a user ID such as a phone number acquired from an external device when a host device such as a portable terminal is shipped or replaced, a change field information processing step 203 is a process for handing over designated change field information to a device unique ID generating step 205. In a user ID externally acquiring step 204, a user ID is acquired from an external device and stored in a host device. In the device unique ID generating step 205, the pieces of information (fixed ID, change field information and user ID) obtained in the encrypted fixed ID decryption processing step 202, the change field information processing step 203 and the user ID externally acquiring step 204 are integrated to generate a device unique ID. In a device unique key generating step 206, a device unique key is generated using the device unique ID generated in the device unique ID generating step 205.

Abstract: An encryption circuit of a secret key cryptosystem which inputs a plain text and a secret key 4A, inputs R partial keys Kn obtained from the secret key 4A and applies repeatedly R times of round operations to the plain text so that the plain text is encrypted including: registers 4G and 4H which store the values after the round operations of the plain text; a fault detection circuit 1A which decides whether a degenerate fault exists or not by the values of the registers 4G and 4H; and a circuit 1B which invalidates the secret key 4A when the degenerate fault exists in the detection result. The invention provides an encryption circuit which can appropriately respond to a new element of causing occurrence of the degenerate fault, suppress the cost of the hardware, and has a measure against the fault analysis while suppressing an increase in an encryption processing time.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.