Patents by Inventor Kentaro Suga
Kentaro Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8653651Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.Type: GrantFiled: February 27, 2012Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Uchida, Takashi Togasaki, Satoru Hara, Kentaro Suga
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Publication number: 20130078766Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.Type: ApplicationFiled: November 14, 2012Publication date: March 28, 2013Inventors: Takao NOGI, Tomoyuki KITANI, Akira TOJO, Kentaro SUGA
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Patent number: 8334173Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separateType: GrantFiled: January 27, 2010Date of Patent: December 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takao Nogi, Tomoyuki Kitani, Akira Tojo, Kentaro Suga
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Publication number: 20120235291Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.Type: ApplicationFiled: February 27, 2012Publication date: September 20, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki UCHIDA, Takashi TOGASAKI, Satoru HARA, Kentaro SUGA
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Patent number: 7888180Abstract: A semiconductor apparatus includes a semiconductor device having electrodes on its opposed frontside and backside, respectively, a first external electrode connected to the electrode at the frontside, the first external electrode having a first major surface generally parallel to the frontside of the semiconductor device, and a first side surface generally perpendicular to the first major surface, and a second external electrode having a second major surface generally parallel to the backside of the semiconductor device, a second side surface generally perpendicular to the second major surface, and a projection protruding perpendicular to the second major surface and connected to the electrode at the backside, The first side surface of the first external electrode and the second side surface of the second external electrode serve as mount surfaces. The semiconductor device is located between the first external electrode and the second external electrode.Type: GrantFiled: May 30, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takao Nogi, Kentaro Suga
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Publication number: 20100233856Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separateType: ApplicationFiled: January 27, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takao NOGI, Tomoyuki Kitani, Akira Tojo, Kentaro Suga
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Publication number: 20080296760Abstract: A semiconductor apparatus includes a semiconductor device having electrodes on its opposed frontside and backside, respectively, a first external electrode connected to the electrode at the frontside, the first external electrode having a first major surface generally parallel to the frontside of the semiconductor device, and a first side surface generally perpendicular to the first major surface, and a second external electrode having a second major surface generally parallel to the backside of the semiconductor device, a second side surface generally perpendicular to the second major surface, and a projection protruding perpendicular to the second major surface and connected to the electrode at the backside, The first side surface of the first external electrode and the second side surface of the second external electrode serve as mount surfaces. The semiconductor device is located between the first external electrode and the second external electrode.Type: ApplicationFiled: May 30, 2008Publication date: December 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takao NOGI, Kentaro Suga
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Patent number: 7205239Abstract: According to a method of manufacturing a semiconductor wafer and a semiconductor device, a rear surface of the semiconductor wafer is ground, and is dry- or wet-etched so that rear surfaces of semiconductor chips on the segmented semiconductor wafer have substantially equal surface roughness. The semiconductor chips are bonded onto a lead frame via bumps using thermo-compression and ultrasonic vibrations.Type: GrantFiled: August 15, 2005Date of Patent: April 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiro Iguchi, Kentaro Suga, Taizo Tomioka
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Publication number: 20060032834Abstract: According to a method of manufacturing a semiconductor wafer and a semiconductor device, a rear surface of the semiconductor wafer is ground, and is dry—or wet—etched so that rear surfaces of semiconductor chips on the segmented semiconductor wafer have substantially equal surface roughness. The semiconductor chips are bonded onto a lead frame via bumps using thermo-compression and ultrasonic vibrations.Type: ApplicationFiled: August 15, 2005Publication date: February 16, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomohiro Iguchi, Kentaro Suga, Taizo Tomioka