Abstract: A digital pattern generator generates various kinds of digital pattern signals. A first memory stores an execution signal, an area control signal and a digital pattern. A program counter generates a first address signal in accordance with the execution signal read from the first memory and a first clock signal, and the first memory is addressed by the first address signal. Thus, the pattern generator operates as a microprogram type generator. A second memory includes a plurality of memory areas each storing a digital pattern, and a capacity of each the memory area corresponds to that of the first memory. When the second memory is addressed by a second address signal from an address counter, the pattern generator operates as a sequential type generator. When the memory area of the second memory is selected by the area control signal read from the first memory and the selected memory area is addressed by the first address signal, the second memory acts as an auxiliary memory of the first memory.

Abstract: A detector circuit for detecting skew or phase shift of at least three logic signals comprises an OR gate for receiving a plurality of logic signals, an exclusive-OR gate for receiving an output signal from the OR gate as well as a reference logic signal, and a pulse width check circuit responsive to the exclusive-OR gate for providing the skew detection result.

Abstract: In a method for testing for probe calibration, a square-wave signal is applied to a probe and a cyclic probe output signal resulting therefrom is compared to a reference level at a plurality of points along one cycle of the output signal. The reference signal is iteratively increased or decreased until it is less than or greater than a minimum or maximum peak magnitude of the probe output signal by a small amount. The probe is then determined to be calibrated according whether the magnitude of the output signal at each point is greater than or less than the reference level.

Abstract: A circuit detects that a plurality of signals are generated in a predetermined sequence. The plurality of signals are applied to address terminals of a memory which has stored therein a predetermined pattern, and a divide-by-N counter (N:positive integer) counts a first data output signal from the memory N times and applies a carry output signal generated as a result thereof to another address terminal of the memory. An output signal of the circuit is derived from a second data output terminal of said memory when the plurality of input signals occur in the predetermined pattern of the memory and the carry signal from the counter is applied to the memory.