Patents by Inventor Kentarou Seki

Kentarou Seki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11118258
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 14, 2021
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Yo Shimazaki, Kentarou Seki, Hiroki Furushou, Chiaki Hatsuta
  • Patent number: 10538838
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa). When the mask body satisifies these inequalities, the generation of recesses during ultrasonic cleaning of the mask can be suppressed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 21, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Yo Shimazaki, Kentarou Seki, Hiroki Furushou, Chiaki Hatsuta
  • Patent number: 10541387
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa). When the mask body satisfies these inequalities, the generation of recesses during ultrasonic cleaning of the mask can be suppressed.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 21, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Yo Shimazaki, Kentarou Seki, Hiroki Furushou, Chiaki Hatsuta
  • Publication number: 20190169733
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).
    Type: Application
    Filed: February 5, 2019
    Publication date: June 6, 2019
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao IKENAGA, Yo SHIMAZAKI, Kentarou SEKI, Hiroki FURUSHOU, Chiaki HATSUTA
  • Publication number: 20180334740
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).
    Type: Application
    Filed: September 29, 2016
    Publication date: November 22, 2018
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao IKENAGA, Yo SHIMAZAKI, Kentarou SEKI, Hiroki FURUSHOU, Chiaki HATSUTA
  • Publication number: 20180277799
    Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).
    Type: Application
    Filed: May 23, 2018
    Publication date: September 27, 2018
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Yo Shimazaki, Kentarou Seki, Hiroki Furushou, Chiaki Hatsuta
  • Patent number: 8525351
    Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 3, 2013
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20110291303
    Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicants: Nitto Denko Corporation, Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 8018044
    Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: September 13, 2011
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 7943427
    Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 17, 2011
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20080048311
    Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.
    Type: Application
    Filed: July 13, 2005
    Publication date: February 28, 2008
    Applicants: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20070241445
    Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.
    Type: Application
    Filed: July 13, 2005
    Publication date: October 18, 2007
    Applicants: DAI NIPPON PRINTING CO., LTD., NITTO DENKO CORPORATION
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura