Abstract: A three-dimensional memory device includes a source-level structure located over a substrate, an alternating stack of insulating layers and electrically conductive layers located over the source-level structure, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. The source-level structure includes a lower source-level semiconductor layer including elongated grooves in an upper portion thereof, doped semiconductor source rails located within the elongated grooves, and an upper source-level semiconductor layer. The doped semiconductor source rails are laterally spaced apart from each other along a first horizontal direction and laterally extend along a second horizontal direction. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel that contacts a respective one of the doped semiconductor source rails.