Patents by Inventor Kento Kitamura

Kento Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387374
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of a source layer, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, a dielectric material portion laterally offset from the alternating stack, a connection via structure vertically extending through the dielectric material portion and contacting a front side surface of a metallic plate, and a backside contact pad in electrical contact with the metallic plate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Masato NOGUCHI, Kento KITAMURA, Yusuke YOSHIDA
  • Publication number: 20240306392
    Abstract: A device structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric material portion overlying the alternating stack, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a coaxial double contact via structure. The coaxial double contact via structure includes an inner layer contact via structure contacting the first-type electrically conductive layer; at least one insulating spacer layer that laterally surrounds the inner layer contact via structure; and an outer layer contact via structure including a tubular conductive portion that laterally surrounds the at least one insulating spacer layer and contacting the second-type electrically conductive layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 12, 2024
    Inventors: Ryo MIZUTSU, Kento KITAMURA, Kentaro YOSHINO, Naoki TAKEGUCHI
  • Patent number: 10008570
    Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 26, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Kento Kitamura, Tong Zhang, Chun Ge, Yanli Zhang, Satoshi Shimizu, Yasuo Kasagi, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Johann Alsmeier, James Kai
  • Patent number: 9991282
    Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 5, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Satoshi Shimizu, Hiroyuki Ogawa, Yasuo Kasagi, Kento Kitamura
  • Publication number: 20180151589
    Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 31, 2018
    Inventors: Satoshi SHIMIZU, Hiroyuki OGAWA, Yasuo KASAGI, Kento KITAMURA
  • Publication number: 20180122906
    Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Jixin YU, Kento KITAMURA, Tong ZHANG, Chun GE, Yanli ZHANG, Satoshi SHIMIZU, Yasuo KASAGI, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Johann ALSMEIER, James KAI
  • Patent number: 9876031
    Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 23, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Satoshi Shimizu, Hiroyuki Ogawa, Yasuo Kasagi, Kento Kitamura