Abstract: An electronic apparatus includes an electric double-layer capacitor and at least one processor that, in response to the capacitor being charged in a first charging mode where a self-discharge amount of the capacitor per unit time after start of self-discharge that is performed after a voltage of the capacitor reaches a predetermined voltage by the capacitor being charged is smaller than a predetermined threshold value, performs a predetermined process in a first mode with electric power supplied from the capacitor, and in response to the capacitor being charged in a second charging mode where the self-discharge amount of the capacitor per unit time after the start of the self-discharge is equal to or larger than the threshold value, performs the process in a second mode where current consumption in performing the process is smaller than current consumption therein in the first mode with the power supplied from the capacitor.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of a source layer, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, a dielectric material portion laterally offset from the alternating stack, a connection via structure vertically extending through the dielectric material portion and contacting a front side surface of a metallic plate, and a backside contact pad in electrical contact with the metallic plate.

Abstract: A device structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric material portion overlying the alternating stack, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a coaxial double contact via structure. The coaxial double contact via structure includes an inner layer contact via structure contacting the first-type electrically conductive layer; at least one insulating spacer layer that laterally surrounds the inner layer contact via structure; and an outer layer contact via structure including a tubular conductive portion that laterally surrounds the at least one insulating spacer layer and contacting the second-type electrically conductive layer.

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.