Abstract: A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration variables to a generic top level model of the phase locked loop to generate a specific configuration of the phase locked loop from the generic top level model; and (c) generating as output a hardware description language code for the specific configuration of the phase locked loop.

Abstract: A method of generating a cell function and timing model library in a standard library format includes the steps of (a) receiving as input a model source file, a technology dependent file, and a cell list data file; (b) parsing a functional description for each cell in the cell list data file from the model source file; (c) expanding parameterized timing data for each cell in the cell list data file from the technology dependent file; and (d) generating as output a cell model library in a standard library format from the parameterized timing data.

Abstract: A method of generating a back-annotated standard delay format file for designing integrated circuits with conditional/moded delays is disclosed that includes the steps of receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated standard delay format file from the output data structure.