Abstract: An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector.

Abstract: Light is converted to an electric signal by performing a light-to-frequency conversion of the light received during a first phase of operation. Following the first phase of operation, a light-to-time conversion is performed on light received during a second phase of operation. Following the second phase of operation a digital representation of the light is generated in response to the light-to-frequency conversion and the light-to-time conversion.

Abstract: A readout circuit for reading from addressable nodes comprises first and second half-circuits of a differential amplifier. The first half-circuit comprises at least one source follower transistor adapted to receive an input signal from one of the addressable nodes, such as pixel readouts of an imaging system. The first half-circuit further comprises a row selector switch coupled to the source follower transistor to selectively activate the source follower transistor to receive the input signal. The second half-circuit comprises an output node for providing an output signal of a readout of a selected addressable node. The second half-circuit further comprises a source leader transistor coupled to the output node to provide a feedback signal based on the readout. A feedback loop is connected to the source leader transistor to provide feedback from the output node for utilization in a differential amplification of the input signal.

Abstract: A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.

Abstract: An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector.

Abstract: A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.

Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal.

Abstract: Light is converted to an electric signal by performing a light-to-frequency conversion of the light received during a first phase of operation. Following the first phase of operation, a light-to-time conversion is performed on light received during a second phase of operation. Following the second phase of operation a digital representation of the light is generated in response to the light-to-frequency conversion and the light-to-time conversion.

Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal.

Abstract: A readout circuit for reading from addressable nodes comprises first and second half-circuits of a differential amplifier. The first half-circuit comprises at least one source follower transistor adapted to receive an input signal from one of the addressable nodes, such as pixel readouts of an imaging system. The first half-circuit further comprises a row selector switch coupled to the source follower transistor to selectively activate the source follower transistor to receive the input signal. The second half-circuit comprises an output node for providing an output signal of a readout of a selected addressable node. The second half-circuit further comprises a source leader transistor coupled to the output node to provide a feedback signal based on the readout. A feedback loop is connected to the source leader transistor to provide feedback from the output node for utilization in a differential amplification of the input signal.