Abstract: Embodiments describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate hardware register. Both Direct Memory Access (DMA) and non-DMA hardware can be supported with the one or more embodiments.

Abstract: Aspects describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate hardware register. Both Direct Memory Access (DMA) and non-DMA hardware can be supported with the one or more aspects. In an aspect, a method is provided for data transmission. The method includes obtaining data comprising one or more logical channels wherein each of the logical channels comprises one or more code blocks, and wherein each of the code blocks comprises one or more turbo groups, organizing the data based on the one or more code blocks to produce time-sequenced turbo groups, and outputting the time-sequenced turbo groups.

Abstract: Multiplexer to transmitter interface protocol. A method for a data interface protocol is provided that includes receiving a first packet stream having at least one overhead information symbol (OIS) group and at least one multicast logical channel (MLC) group, and mapping each OIS group to an OIS descriptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payload packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes input logic to receive the first packet stream, processing logic to map each OIS group to an OIS descriptor packet an OIS payload packet, and each MLC group to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.

Abstract: Aspects describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate hardware register. Both Direct Memory Access (DMA) and non-DMA hardware can be supported with the one or more aspects. In an aspect, a method is provided for data transmission. The method includes obtaining data comprising one or more logical channels wherein each of the logical channels comprises one or more code blocks, and wherein each of the code blocks comprises one or more turbo groups, organizing the data based on the one or more code blocks to produce time-sequenced turbo groups, and outputting the time-sequenced turbo groups.

Abstract: Embodiments describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate hardware register. Both Direct Memory Access (DMA) and non-DMA hardware can be supported with the one or more embodiments.