Abstract: A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, and includes a single read port for outputting the data. The hardware arrangement includes a modified sense amplifier (SA) configured to receive the data output on the single read port, and directly receive the plurality of decoded uncommon memory address portions. The plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA. Data output from the memory bitcell is forwarded when the modified SA is enabled.

Abstract: A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, and includes a single read port for outputting the data. The hardware arrangement includes a modified sense amplifier (SA) configured to receive the data output on the single read port, and directly receive the plurality of decoded uncommon memory address portions. The plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA. Data output from the memory bitcell is forwarded when the modified SA is enabled.

Abstract: A hardware implemented method for resolving collisions of memory addresses of a memory array is provided. In this hardware implemented method, a read memory address is compared with a write memory address. If the read and write memory addresses match, write data is directed from a data input to a data output, whereby the data input is further configured to input the write data to the memory array. A system and a memory chip for resolving collisions of memory addresses of a memory array are also described.

Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

Abstract: A first sense amp circuit includes a pre-charge circuit, a keeper circuit, a select device and a driver device. The pre-charge circuit coupled to an input data line, the input data line being coupled to an input of a first inverter. The keeper circuit coupled in parallel with the first inverter. The select device coupled to a discharge path of the first inverter. The driver device coupled in parallel to an output data line of the first inverter.

Abstract: A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the pipeline immediately following the first swap request. The first swap request and the second swap request are examined to determine if the first swap request and the second swap request swap a same register.