Abstract: Provided is a binder composition for a secondary battery with which a slurry composition for a secondary battery having low foaming can be produced, and that can improve handleability of a functional layer or electrode layer formed using the produced slurry composition for a secondary battery. The binder composition for a secondary battery contains a polymer A and a solvent. The polymer A includes an amide group-containing monomer unit and a carboxylic acid ester-containing monomer unit including an alkyl chain having a carbon number of not less than 2 and not more than 9. Content of the carboxylic acid ester-containing monomer unit in the polymer A is not less than 12 mass % and not more than 28 mass %.

Abstract: An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The described embodiments of the present invention provide a method in which the circuit configuration of redundancy circuitry in a random access memory can be simplified and the setting operation of the address of the defective memory cell is also simplified. In one described embodiment, the redundant circuit includes a fuse decoder (11), which functions as the address-generating circuit for the address of the defective memory cell, and a latch circuit (21). A write operation to the defective memory cell on the write port containing the fuse decoder (11) causes the address of the defective cell to be stored in the latch circuit. Each input/output port, except the input port using the fuse decoder, includes a comparator (22) for comparing the address for an operation on the respective port to the address stored in the latch circuit.

Abstract: This invention provides a FIFO memory device having a simple circuit structure without using a cache memory, and line buffers used in the FIFO memory device having a simplified circuit structure.The FIFO memory device comprises a read line buffer (5) having a two-step structure in place of a cache memory which stores and outputs the first data. The read line buffer (5) outputs the data from the memory array (4). Namely, the read line buffer (5) comprises first-step master latch circuits (33) and (34) and a second-step slave latch circuit (37), and the single master latch circuit (33) functions equivalent to the cache memory. In addition, the number of line buffers is reduced by multiplying the selection of memory array (4) bit lines (BL) using transfer gates (11-14).