Patents by Inventor Kenya Hironaga
Kenya Hironaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10050011Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: GrantFiled: January 25, 2017Date of Patent: August 14, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
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Publication number: 20170162539Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: ApplicationFiled: January 25, 2017Publication date: June 8, 2017Inventors: Kenya HIRONAGA, Masatoshi YASUNAGA, Tatsuya HIRAI, Soshi KURODA
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Patent number: 9589923Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: GrantFiled: August 31, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
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Publication number: 20150371967Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Kenya HIRONAGA, Masatoshi YASUNAGA, Tatsuya HIRAI, Soshi KURODA
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Patent number: 9130062Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: GrantFiled: September 12, 2013Date of Patent: September 8, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
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Patent number: 9087816Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).Type: GrantFiled: February 26, 2014Date of Patent: July 21, 2015Assignee: Renesas Electronics CorporationInventors: Soshi Kuroda, Kenya Hironaga, Hironori Matsushima, Masatoshi Yasunaga, Akira Yamazaki
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Patent number: 9024454Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.Type: GrantFiled: June 2, 2014Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga, Soshi Kuroda
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Publication number: 20140273353Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.Type: ApplicationFiled: June 2, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masatoshi YASUNAGA, Hironori MATSUSHIMA, Kenya HIRONAGA, Soshi KURODA
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Patent number: 8772952Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.Type: GrantFiled: September 23, 2010Date of Patent: July 8, 2014Assignee: Renesas Electronics CorporationInventors: Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga, Soshi Kuroda
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Publication number: 20140175678Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: Renesas Electronics CorporationInventors: Soshi Kuroda, Kenya Hironaga, Hironori Matsushima, Masatoshi Yasunaga, Akira Yamazaki
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Patent number: 8692383Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).Type: GrantFiled: September 13, 2011Date of Patent: April 8, 2014Assignee: Renesas Electronics CoporationInventors: Soshi Kuroda, Kenya Hironaga, Hironori Matsushima, Masatoshi Yasunaga, Akira Yamazaki
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Publication number: 20140073068Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: ApplicationFiled: September 12, 2013Publication date: March 13, 2014Applicant: Renesas Electronics CorporationInventors: Kenya HIRONAGA, Masatoshi YASUNAGA, Tatsuya HIRAI, Soshi KURODA
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Patent number: 8629002Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.Type: GrantFiled: October 26, 2012Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
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Patent number: 8605277Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (?). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.Type: GrantFiled: September 24, 2011Date of Patent: December 10, 2013Assignee: Renesas Electronics CorporationInventors: Satoshi Yamada, Takashi Karashima, Kenya Hironaga, Masatoshi Yasunaga, Yuji Fujimoto
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Patent number: 8334172Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.Type: GrantFiled: February 9, 2011Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
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Publication number: 20120081702Abstract: Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (?). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.Type: ApplicationFiled: September 24, 2011Publication date: April 5, 2012Inventors: Satoshi YAMADA, Takashi KARASHIMA, Kenya HIRONAGA, Masatoshi YASUNAGA, Yuji FUJIMOTO
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Publication number: 20120061850Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).Type: ApplicationFiled: September 13, 2011Publication date: March 15, 2012Inventors: Soshi KURODA, Kenya Hironaga, Hironori Matsushima, Masatoshi Yasunaga, Akira Yamazaki
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Publication number: 20110201155Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.Type: ApplicationFiled: February 9, 2011Publication date: August 18, 2011Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
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Publication number: 20110074019Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Inventors: Masatoshi YASUNAGA, Hironori Matsushima, Kenya Hironaga, Soshi Kuroda
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Publication number: 20100320623Abstract: A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved.Type: ApplicationFiled: June 2, 2010Publication date: December 23, 2010Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga