Patents by Inventor Kenya Iwasaki
Kenya Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11035741Abstract: A temperature measurement substrate according to an embodiment of the present disclosure includes: a substrate which is any one of a semiconductor wafer and a substrate for a flat panel display; and at least one optical fiber laid on a surface of the substrate and having a first pattern portion and a second pattern portion formed more densely than the first pattern portion.Type: GrantFiled: April 6, 2017Date of Patent: June 15, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Tadashi Mitsunari, Satoshi Tanaka, Tsuyoshi Moriya, Toshiya Matsuda, Masaaki Miyagawa, Kenya Iwasaki
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Publication number: 20210143044Abstract: A plasma processing apparatus includes: a vacuumable processing container; a lower electrode provided inside the processing container and for placing a substrate thereon; an edge ring arranged to surround a periphery of the substrate; an electrostatic chuck provided on the lower electrode to attract the substrate and the edge ring; a heat-transfer-gas supply part for supplying a heat transfer gas between the electrostatic chuck and the edge ring through one or more first through-holes respectively formed in the lower electrode and the electrostatic chuck; and a heat-transfer-gas exhaust part for exhausting the heat transfer gas between the electrostatic chuck and the edge ring through one or more second through-holes respectively formed in the lower electrode and the electrostatic chuck. Electrostatic chuck openings of the second through-holes are formed radially inward of those of the first through-holes between the electrostatic chuck and the edge ring.Type: ApplicationFiled: November 3, 2020Publication date: May 13, 2021Inventors: Shinsuke OKA, Kenya IWASAKI, Hideto SAITO
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Publication number: 20190120703Abstract: A temperature measurement substrate according to an embodiment of the present disclosure includes: a substrate which is any one of a semiconductor wafer and a substrate for a flat panel display; and at least one optical fiber laid on a surface of the substrate and having a first pattern portion and a second pattern portion formed more densely than the first pattern portion.Type: ApplicationFiled: April 6, 2017Publication date: April 25, 2019Applicant: TOKYO ELECTRON LIMITEDInventors: Tadashi MITSUNARI, Satoshi TANAKA, Tsuyoshi MORIYA, Toshiya MATSUDA, Masaaki MIYAGAWA, Kenya IWASAKI
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Patent number: 9318387Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes separating each of the semiconductor devices or semiconductor integrated circuits. Each of the separated semiconductor devices or semiconductor integrated circuits is non-rectangular shaped, and the step of separating each of the semiconductor devices or semiconductor integrated circuits is performed by dry etching.Type: GrantFiled: October 23, 2015Date of Patent: April 19, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Publication number: 20160042999Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes separating each of the semiconductor devices or semiconductor integrated circuits. Each of the separated semiconductor devices or semiconductor integrated circuits is non-rectangular shaped, and the step of separating each of the semiconductor devices or semiconductor integrated circuits is performed by dry etching.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 9196539Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer. The mask pattern is a repeated pattern without having a lattice line shape, and the step of separating each of the semiconductor devices or semiconductor integrated circuits is performed by plasma etching.Type: GrantFiled: September 2, 2014Date of Patent: November 24, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Publication number: 20150158242Abstract: An imprint device includes a template provided with a plate-shaped template body and a pattern portion having a predetermined shape formed on a surface of the template body; a template holding mechanism configured to hold the template; a substrate holding mechanism configured to hold a substrate formed with a resin layer made of a photo-curable resin in a state where the pattern portion of the template and the resin layer are in contact with each other; and a light irradiating mechanism configured to irradiate a light in a wavelength range for curing the photo-curable resin. The template allows the light to be incident from a lateral surface of the template body, and the light irradiating mechanism irradiates the light to the resin layer by allowing the light to be incident from the lateral surface of the template body and transmitted through the template body.Type: ApplicationFiled: May 30, 2013Publication date: June 11, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Kenya Iwasaki, Hiroaki Fusano, Takaaki Hirooka, Takeshi Nagao, Hiroyuki Nakayama
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Publication number: 20140370688Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer. The mask pattern is a repeated pattern without having a lattice line shape, and the step of separating each of the semiconductor devices or semiconductor integrated circuits is performed by plasma etching.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 8841141Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes: forming, on a surface of the wafer, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. The line-shaped pattern is formed so as to prevent a test device formed on a gap between the semiconductor devices or semiconductor integrated circuits from remaining on separated semiconductor devices or semiconductor integrated circuits.Type: GrantFiled: January 10, 2014Date of Patent: September 23, 2014Assignee: Tokyo Electron LimitedInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Publication number: 20140127839Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes: forming, on a surface of the wafer, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. The line-shaped pattern is formed so as to prevent a test device formed on a gap between the semiconductor devices or semiconductor integrated circuits from remaining on separated semiconductor devices or semiconductor integrated circuits.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: Tokyo Electron LimitedInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 8658436Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.Type: GrantFiled: April 19, 2011Date of Patent: February 25, 2014Assignee: Tokyo Electron LimitedInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Publication number: 20110281377Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.Type: ApplicationFiled: April 19, 2011Publication date: November 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 7769617Abstract: A worker management system, which includes a plant 100 divided into a plurality of work areas each in correspondence to specific task contents, a database 220 having stored therein task identification information correlating each work area 112 with contents of tasks performed therein and worker detection sensors 130 installed in each work area, identifies the specific work area where a worker is currently located based upon outputs from the worker detection means and then identifies the task currently performed by the worker based upon the task identification information. Based upon the current task thus identified, a decision is made as to whether the worker should continue the current task or be assigned a new task and an instruction for task execution is issued to the worker. Therefore the identification of current tasks, the assignment of a new task and the task reassignment are facilitated to improve the work efficiency.Type: GrantFiled: April 29, 2005Date of Patent: August 3, 2010Assignee: Tokyo Electron LimitedInventors: Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 7682517Abstract: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The surface damaged layer that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: GrantFiled: February 14, 2006Date of Patent: March 23, 2010Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Kenya Iwasaki
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Patent number: 7622392Abstract: A method of processing a substrate that enables the amount removed of an insulating film to be controlled precisely, without damaging an electronic device. An insulating film on a substrate of a solid-state imaging device is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: GrantFiled: February 21, 2006Date of Patent: November 24, 2009Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Kenya Iwasaki
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Patent number: 7510972Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: GrantFiled: February 14, 2006Date of Patent: March 31, 2009Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Kenya Iwasaki
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Publication number: 20060194435Abstract: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The surface damaged layer that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: ApplicationFiled: February 14, 2006Publication date: August 31, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Kenya Iwasaki
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Publication number: 20060191865Abstract: A method of processing a substrate that enables the amount removed of an insulating film to be controlled precisely, without damaging an electronic device. An insulating film on a substrate of a solid-state imaging device is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: ApplicationFiled: February 21, 2006Publication date: August 31, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Kenya Iwasaki
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Publication number: 20060189138Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: ApplicationFiled: February 14, 2006Publication date: August 24, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Kenya Iwasaki
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Publication number: 20050209902Abstract: A worker management system, which includes a plant 100 divided into a plurality of work areas each in correspondence to specific task contents, a database 220 having stored therein task identification information correlating each work area 112 with contents of tasks performed therein and worker detection sensors 130 installed in each work area, identifies the specific work area where a worker is currently located based upon outputs from the worker detection means and then identifies the task currently performed by the worker based upon the task identification information. Based upon the current task thus identified, a decision is made as to whether the worker should continue the current task or be assigned a new task and an instruction for task execution is issued to the worker. Therefore the identification of current tasks, the assignment of a new task and the task reassignment are facilitated to improve the work efficiency.Type: ApplicationFiled: April 29, 2005Publication date: September 22, 2005Inventors: Kenya Iwasaki, Hiroshi Nishikawa