Abstract: A semiconductor device includes a substrate, a channel layer provided on the substrate, a semiconductor layer provided on the channel layer, gate fingers and a gate connection wiring provided on the semiconductor layer, and an insulating film provided between the semiconductor layer and the gate fingers, wherein the gate fingers includes a first gate finger, and a second gate finger closer to the center of the gate fingers in an arrangement direction than the first gate finger, wherein a first distance between a lower surface of the first gate finger in contact with the insulating film and an upper surface of the channel layer in contact with the semiconductor layer is greater than a second distance between a lower surface of the second gate finger in contact with the insulating film and the upper surface of the channel layer in contact with the semiconductor layer.

Abstract: A method of manufacturing a high electron mobility transistor in a furnace, the method including steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.

Abstract: A semiconductor device includes a semiconductor layer provided on a substrate and including a channel layer, a source region connected to the channel layer and having a sheet resistance smaller than a sheet resistance of the channel layer, a drain region connected to the channel layer and having a sheet resistance smaller than the sheet resistance of the channel layer, a plurality of gates provided between the source region and the drain region, arranged in a direction intersecting an arrangement direction of the source region and the drain region, and embedded from an upper surface of the semiconductor layer to at least the channel layer, wherein a part of the source region has a convexity that faces a region between two adjacent gates among the plurality of gates, and protrudes toward a part of the drain region through the region between the two adjacent gates.

Abstract: With respect to a method of simulating a capacitance-voltage (C-V) characteristic of a laminated structure that includes a semiconductor, an insulator provided on the semiconductor, and a metal provided on the insulator, and that includes multiple discrete interface states, at which electrons are trapped or emitted in response to a change of a voltage applied to the metal, at an interface between the semiconductor and the insulator, the method includes calculating a first capacitance in accordance with a first voltage applied to the metal, and calculating a second capacitance from a quantity of electrons emitted from a first interface state corresponding to the first voltage among the multiple discrete interface states. The calculating of the second capacitance includes changing the first voltage in stages and shifting the first interface state in stages.

Abstract: A method of manufacturing a high electron mobility transistor, comprising steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.