Patents by Inventor Kenya Tachibana

Kenya Tachibana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220175000
    Abstract: There is provided a water-soluble additive composition including a cyclic carboxylic acid, the water-soluble additive composition satisfying at least one of the following Conditions 1 to 4: (Condition 1) component (A) the cyclic carboxylic acid, which is other than the following component (B1), and component (B1) one or more selected from the group consisting of gallic acid and an ester thereof are included; (Condition 2) the total content of Na+ and NH4+ is equal to or more than 100 ppm and equal to or less than 5000 ppm with respect to the cyclic carboxylic acid; (Condition 3) the total inorganic ion content (excluding hydrogen ions and hydroxyl group ions) is equal to or more than 300 ppm and equal to or less than 5000 ppm with respect to the cyclic carboxylic acid; and (Condition 4) component (A) the cyclic carboxylic acid, which is other than the following component (B2), and component (B2) an amino acid are included.
    Type: Application
    Filed: March 23, 2020
    Publication date: June 9, 2022
    Inventors: Ryuichi Murata, Yusuke Inoue, Daisuke Fujiwara, Kenya Tachibana, Hiroyuki Miyauchi
  • Publication number: 20210236444
    Abstract: The medicinal product of the present invention contains, as an active ingredient, at least one of a cyclic carboxylic acid compound derived from a plant-derived saccharide and a microorganism, and a derivative thereof. Further, it is preferable that the cyclic carboxylic acid compound is a compound represented by Formula (1).
    Type: Application
    Filed: August 14, 2019
    Publication date: August 5, 2021
    Inventors: Yusuke Inoue, Daisuke Fujiwara, Kenya Tachibana, Hiroyuki Miyauchi
  • Patent number: 8592994
    Abstract: A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: November 26, 2013
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Kenya Tachibana, Masahiro Wada, Hitoshi Kawaguchi, Kensuke Nakamura
  • Publication number: 20130058062
    Abstract: A method for manufacturing a base material having a gold-plated metal fine pattern is disclosed, comprising the steps of preparing a base material having a supporting surface made of a resin; forming a primer resin layer having surface roughness of 0.5 ?m or less on the supporting surface, and forming a metal fine pattern thereon by an SAP process to obtain a base material having a metal fine pattern; and applying a gold-plating treatment to at least one part of a surface of the metal fine pattern; wherein the base material having a metal fine pattern is subjected to a palladium removal treatment in an optional stage before carrying out the gold-plating treatment.
    Type: Application
    Filed: May 26, 2011
    Publication date: March 7, 2013
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Kenya Tachibana, Teppei Ito, Yasuaki Mitsui
  • Patent number: 8008767
    Abstract: The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: August 30, 2011
    Assignee: Sumitomo Bakelight Co., Ltd.
    Inventors: Masahiro Wada, Hiroyuki Tanaka, Hiroshi Hirose, Teppei Itoh, Kenya Tachibana
  • Publication number: 20110180208
    Abstract: A method for laminating a prepreg contributing to decrease in layer thickness and having high productivity, a method for producing a printed wiring board by the method for laminating the prepreg, and a prepreg roll used for the method for laminating the prepreg are provided.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 28, 2011
    Inventors: Kenya TACHIBANA, Kuniharu UMENO, Kenichi KANEDA
  • Publication number: 20110051387
    Abstract: An object of the present invention is to provide an electroless nickel-palladium-gold plating method which is able, when performed on a plating target surface such as terminals of a printed wiring board, terminals of other electronic components, and other resin substrates with a fine metal pattern, to prevent abnormal metal deposition on a resin surface which is an undercoat and to provide a high-quality plated surface. Another object of the present invention is to provide a plated product with a high-quality plated surface, particularly such as an interposer and motherboard, and a semiconductor apparatus using the same.
    Type: Application
    Filed: August 9, 2010
    Publication date: March 3, 2011
    Applicant: SUMITOMO BAKELITE COMPANY, LTD.
    Inventors: Kenya TACHIBANA, Teppei ITO, Yasuaki MITSUI
  • Patent number: 7893542
    Abstract: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 22, 2011
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Kenya Tachibana, Masahiro Wada, Takuya Hatao
  • Publication number: 20100032826
    Abstract: A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.
    Type: Application
    Filed: December 5, 2007
    Publication date: February 11, 2010
    Applicant: SUMITOMO BAKELITE COMPANY LIMITED
    Inventors: Kenya Tachibana, Masahiro Wada, Hitoshi Kawaguchi, Kensuke Nakamura
  • Publication number: 20090273073
    Abstract: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C.
    Type: Application
    Filed: March 28, 2008
    Publication date: November 5, 2009
    Inventors: Kenya Tachibana, Masahiro Wada, Takuya Hatao
  • Publication number: 20090267212
    Abstract: The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.
    Type: Application
    Filed: September 5, 2007
    Publication date: October 29, 2009
    Inventors: Masahiro Wada, Hiroyuki Tanaka, Hiroshi Hirose, Teppei Itoh, Kenya Tachibana