Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: A photoelectric current caused by extraneous light is suppressed and variations in characteristics (for example, a threshold voltage) of a thin film transistor are reduced. An active layer (semiconductor layer) made of polycrystalline silicon, which is transformed from amorphous silicon by laser annealing, is formed on an insulating substrate. A drain region 2d and a source region 2s, which are facing to each other, are formed in the active layer. Each of the drain region 2d and the source region 2s is formed of an n? layer and an n+ layer adjacent to each other. A p-type channel region 2c is formed between the n? layer in the drain region 2d and the n? layer in the source region 2s. A light-shielding layer 3d is formed to cover only a boundary region between the n? layer in the drain region 2d and the channel region 2c to shield the boundary region from extraneous light incident upon the boundary region through the insulating substrate.

Abstract: Each pixel has a display element, a pixel transistor which controls an operation of the display element, and a storage capacitor which stores charges corresponding to display data for a predetermined period. During a normal operation, a capacitor signal to be output to a capacitor line connected to each storage capacitor is AC driven in a predetermined period to improve display quality or the like. A structure to fix the capacitor signal to be output to the capacitor line to a fixed level during defect inspection of the pixel or the like is formed on a substrate simultaneously with a pixel circuit or the like. With this structure, the inspection precision can be improved when the defect inspection of each pixel is to be detected from capacitance value data or the like in each pixel. It is also possible to allow setting of the fixed level in the inspection to an arbitrary inspection voltage suitable for the inspection.

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: There is provided a display which can prevent image deterioration. The display is provide with a shift register circuit including a first circuit part comprising a first transistor of first conductivity type connected to a first potential side and turned on in response to a clock signal, a second transistor of first conductivity type connected to a second potential side, a third transistor of first conductivity type connected between a gate of the first transistor and the second potential and a high resistance connected between the gate of the first transistor and a clock signal line.

Abstract: A write control circuit that generates a control signal to initiate a write operation for a semiconductor memory device, such as an EEPROM, compensates for fluctuations in the supply voltage. The write control circuit includes a control potential generator that produces a first control potential which is kept higher than the ground potential and a second control potential which is kept lower than the supply potential. A first transistor is connected to the supply potential and receives a write potential at its gate. A second transistor is connected between the first transistor and ground and receives the first control potential at its gate. A third transistor is connected to the supply potential and receives the second control potential at its gate. A fourth transistor is connected between the third transistor and ground and receives a potential from a first node between the first and second transistors at its gate. The control signal is generated at a second node between the third and fourth transistors.