Patents by Inventor Kenzo Kawano

Kenzo Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6476313
    Abstract: A solar cell including a semiconductor substrate of a first conductive type; a first region of a second conductive type provided on a surface of the substrate; and a bypass function region including a second region of a second conductive type provided on the surface of the substrate and spaced a predetermined distance from the first region, and a third region for setting the substrate and the second region at the same potential; wherein when a reverse voltage is applied between the substrate and the first region, the bypass function region forms a bypass circuit between the substrate and the first region using a depletion layer formed inside the substrate by the reverse voltage.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: November 5, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kenzo Kawano
  • Publication number: 20020007846
    Abstract: A solar cell including a semiconductor substrate of a first conductive type; a first region of a second conductive type provided on a surface of the substrate; and a bypass function region including a second region of a second conductive type provided on the surface of the substrate and spaced a predetermined distance from the first region, and a third region for setting the substrate and the second region at the same potential; wherein when a reverse voltage is applied between the substrate and the first region, the bypass function region forms a bypass circuit between the substrate and the first region using a depletion layer formed inside the substrate by the reverse voltage.
    Type: Application
    Filed: May 22, 2001
    Publication date: January 24, 2002
    Inventor: Kenzo Kawano
  • Patent number: 6127623
    Abstract: A solar cell comprises a crystalline substrate having projections and depressions formed on either side or both sides of the substrate, wherein a projection-depression depth is 25 .mu.m or more.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: October 3, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuyo Nakamura, Kenzo Kawano, Hidetoshi Washio, Yoshifumi Tonomura, Kunio Kamimura, Hideyuki Ueyama
  • Patent number: 4926243
    Abstract: A high voltage MOS field-effect semiconductor device comprising, as formed on a single seimconductor substrate a high voltage first MOS field-effect transistor and a conventional second MOS field-effect transistor operable at a lower voltage than the first transistor. The semiconductor substrate is covered with an aluminum or like conductor layer over the region thereof where the conventional second field-effect transistor is located.
    Type: Grant
    Filed: March 9, 1988
    Date of Patent: May 15, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyotoshi Nakagawa, Kenzo Kawano