Abstract: A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

Abstract: A display device (2) includes a processor (13) that outputs drawing data and a timing controller (11) that outputs the drawing data input from the processor according to horizontal synchronization and vertical synchronization. When a still image region where drawing data has not been updated compared with a previous frame and a moving image region where drawing data has been updated compared with a previous frame are included in one frame, the processor transmits data update information, which is for specifying the position of the moving image region or a line including the moving image region, to the timing controller temporally earlier than drawing data of the line including the moving image region. The timing controller performs processing for lowering the frame rate of the still image region or processing for thinning out some of image lines of the still image region based on the data update information.

Abstract: A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

Abstract: A display device (2) includes a processor (13) that outputs drawing data and a timing controller (11) that outputs the drawing data input from the processor according to horizontal synchronization and vertical synchronization. When a still image region where drawing data has not been updated compared with a previous frame and a moving image region where drawing data has been updated compared with a previous frame are included in one frame, the processor transmits data update information, which is for specifying the position of the moving image region or a line including the moving image region, to the timing controller temporally earlier than drawing data of the line including the moving image region. The timing controller performs processing for lowering the frame rate of the still image region or processing for thinning out some of image lines of the still image region based on the data update information.

Abstract: A semiconductor integrated circuit having one or more functional circuit blocks and executing a set of instructions is configured so as to change the operating frequency or halt operation of said one or more functional circuit blocks for each instruction or execution cycle. Another semiconductor integrated circuit, having a plurality of internal or external memory blocks or an internal or external single memory block that can be dealt with as a plurality of logical memory blocks and executing a set of instructions, is configured so as to change the operating frequency according to the performance of the memory block for each instruction or execution cycle so that the operating speed during data access time in execution cycle can be changed.

Abstract: A semiconductor integrated circuit having one or more functional circuit blocks and executing a set of instructions is configured so as to change the operating frequency or halt operation of said one or more functional circuit blocks for each instruction or execution cycle. Another semiconductor integrated circuit, having a plurality of internal or external memory blocks or an internal or external single memory block that can be dealt with as a plurality of logical memory blocks and executing a set of instructions, is configured so as to change the operating frequency according to the performance of the memory block for each instruction or execution cycle so that the operating speed during data access time in execution cycle can be changed.

Abstract: A polyazo dye represented by the formula ##SPC1##Wherein A is an optionally substituted aromatic ring; B is an aromatic ring having at least one substituent selected from the group consisting of amino, substituted amino and hydroxy; Y is hydrogen, alkali metal, --NH.sub.4 or amine salt residue; n is 1 or 2; and one of R.sup.1 and R.sup.2 is hydroxy and the other is amino.

Abstract: A polyazo dye represented by the formula ##SPC1##Wherein A is an aromatic ring having or not having a substituent, B is an aromatic ring having at least one substituent selected from the group consisting of amino, substituted amino and hydroxyl, Y is hydrogen, alkali metal, --NH.sub.4 or an amine salt residue, n is 1 or 2, and each of R.sup.1 and R.sup.2 is hydroxyl or amino, R.sup.1 being amino when R.sup.2 is hydroxyl and hydroxyl when R.sup.2 is amino. The polyazo dye has outstanding utility in the dyeing of fibers having hydroxyl and/or amide groups and are not carcinogenic.