Abstract: A semiconductor memory device includes a semiconductor layer extending in a first direction, a conductive layer opposed to the semiconductor layer in a second direction intersecting with the first direction, an electric charge accumulating layer disposed between the semiconductor layer and the conductive layer, a first insulating layer disposed between the semiconductor layer and the electric charge accumulating layer, and a second insulating layer disposed between the conductive layer and the electric charge accumulating layer. The semiconductor layer includes at least one protrusion protruding in the second direction toward the electric charge accumulating layer. A position in the first direction of the protrusion is inside with respect to corner portions at both ends in the first direction of a surface opposed to the semiconductor layer in the electric charge accumulating layer.

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Abstract: A semiconductor device includes a stacked body, a columnar portion and a barrier film. The stacked body includes a plurality of insulating layers and a plurality of electrode layers including aluminum stacked alternately along a first direction. The columnar portion is provided inside the stacked body and extends in the first direction. The columnar portion includes a semiconductor body, a tunneling insulating film, a blocking insulating film and a charge storage portion. The semiconductor body extends in the first direction. The tunneling insulating film is provided between the semiconductor body and the stacked body. The blocking insulating film is provided between the tunneling insulating film and the stacked body. The charge storage portion is provided between the tunneling insulating film and the blocking insulating film. The barrier film includes a metal silicide, and is provided between the blocking insulating film and one of the plurality of electrode layers.

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Abstract: A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.

Abstract: A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.

Abstract: A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract: A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.

Abstract: Replacement metal gates well suited for self-aligned contact formation are made by replacing the dummy gate with a recessed polysilicon layer and then effecting an aluminum-polysilicon substitution. The resulting upper polysilicon layer is easily removed from the recessed aluminum layer, which can then be protected with a protective dielectric layer for subsequent formation of a source or drain contact hole.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract: A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.

Abstract: A semiconductor device improves a Schottky-barrier field-effect transistor. In a semiconductor device including a gate electrode formed with interposition of a gate insulating film on a channel formed on a semiconductor substrate, and a Schottky source/drain formed within a top surface of the substrate to be positioned on both sides of the gate insulating film so that end portions of the Schottky source and the Schottky drain do not cover a lower end portion of the gate insulating film and so as to form Schottky junctions with the semiconductor substrate, a Schottky barrier height at an interface between the end portion of the Schottky source and the semiconductor substrate and a Schottky barrier height at an interface between the end portion of the Schottky drain and the semiconductor substrate are different from Schottky barrier heights at interfaces between portions except the end portions of the Schottky source/drain and the substrate.

Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.

Abstract: A semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A method of manufacturing a semiconductor device including introducing nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.

Abstract: A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.

Abstract: Replacement metal gates well suited for self-aligned contact formation are made by replacing the dummy gate with a recessed polysilicon layer and then effecting an aluminum-polysilicon substitution. The resulting upper polysilicon layer is easily removed from the recessed aluminum layer, which can then be protected with a protective dielectric layer for subsequent formation of a source or drain contact hole.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.