Patents by Inventor Kenzo Nishide

Kenzo Nishide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9208425
    Abstract: An RFID tag including an inlay having a sheet-like shape and including an antenna and an IC chip electrically connected to the antenna, an outer covering member that covers the inlay, the outer covering member having a planar shape and including a main surface and a rear surface, and a frame part arranged on at least one of the main surface and the rear surface. The frame part is erected in a thickness direction of the outer covering member. The frame part surrounds the IC chip in a plan view.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: December 8, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Kenzo Nishide, Shigeru Gotou, Noritsugu Ozaki, Shunji Baba
  • Publication number: 20150060554
    Abstract: An RFID tag including an inlay having a sheet-like shape and including an antenna and an IC chip electrically connected to the antenna, an outer covering member that covers the inlay, the outer covering member having a planar shape and including a main surface and a rear surface, and a frame part arranged on at least one of the main surface and the rear surface. The frame part is erected in a thickness direction of the outer covering member. The frame part surrounds the IC chip in a plan view.
    Type: Application
    Filed: August 15, 2014
    Publication date: March 5, 2015
    Inventors: Takayoshi Matsumura, Kenzo NISHIDE, Shigeru Gotou, NORITSUGU OZAKI, Shunji Baba
  • Publication number: 20060198629
    Abstract: It is an object of the present invention to improve mechanical durability of a portable display device using cholesteric liquid crystal with a memory function such as a non-contact IC card. A display element comprising two substrates 1 which oppose each other and a display portion (liquid crystal) 2 which is sandwiched by the substrates 1, comprises a wall structure 3 bearing a substrate on portions other than the display portion 2, in which the wall is perpendicular to the substrate 1 and a surface perpendicular to the wall is adhered to the substrate 1. Further, in the above display element, an area of the surface which is adhered to the substrate 1 is larger than an area of a surface of the display portion 2 which faces the substrate 1.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 7, 2006
    Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITED
    Inventors: Junji Tomita, Masaki Nose, Tomohisa Shingai, Fumio Yamagishi, Shigeru Hashimoto, Yoshiyasu Sugimura, Yoshikazu Yabe, Futoshi Kisuno, Takahiro Hirano, Kenzo Nishide, Shunji Baba
  • Publication number: 20060176410
    Abstract: In an IC card, cholesteric liquid crystal layers reflecting red light and a cholesteric liquid crystal layer reflecting blue light, in a planar state, are laminated, and a voltage is respectively applied to the laminated cholesteric liquid crystal layers, to change the orientation of the cholesteric liquid crystals between the planar state and a focal conic state, so as to transmit or reflect light, thereby displaying predetermined information.
    Type: Application
    Filed: March 3, 2006
    Publication date: August 10, 2006
    Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITED
    Inventors: Masaki Nose, Junji Tomita, Tomohisa Shingai, Fumio Yamagishi, Kenzo Nishide, Shigeru Hashimoto, Yoshiyasu Sugimura, Yoshikazu Yabe, Futoshi Kisuno, Takahiro Hirano
  • Patent number: 6522159
    Abstract: A setting of a logical state in an integrated circuit is changed, a plurality of measurement patterns which are used in a quiescent power source current test of the integrated circuit are formed, an internal state value 0/1 of each net at the time when the measurement patterns are supplied by a simulation of the integrated circuit is derived, and further, a pass or fail test result is obtained every measurement pattern by the quiescent power source current test in which a plurality of measurement patterns were supplied to the integrated circuit determined to be a defective device. A state value variable in which the internal state values of all measurement patterns have been stored every net and a test result variable in which the pass or fail test result has been stored every measurement pattern are formed on the basis of those measurement patterns, internal state values, and test results.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: February 18, 2003
    Assignee: Fujitsu Limited
    Inventor: Kenzo Nishide