Patents by Inventor Kenzou Hatada

Kenzou Hatada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
    Patent number: 6323663
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: November 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
    Patent number: 6005401
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: December 21, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
    Patent number: 5945834
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Method for attaching semiconductors to a transparent substrate using a light-curable resin
    Patent number: 5037780
    Abstract: A method for fabricating semiconductor devices comprising pressing first and second semiconductor devices against a transparent board at different times by means of first and second pressure tools that are separate from each other and move upward and downward independent of each other so that a difference in thickness between the devices and a deflection of the devices can be absorbed and a reliable electrical connection between the electrodes of the devices and the conductors of the board can be attained, which makes it possible to continuously achieve a highly dense assembly of semiconductor devices with a minute gap therebetween.
    Type: Grant
    Filed: February 1, 1990
    Date of Patent: August 6, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Kenzou Hatada, Yoshinobu Takeshita, Kazuya Otani, Koji Hidaka, Tsuguo Sakiyama