Patents by Inventor KeoChang Lee

KeoChang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418332
    Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Goo Lee, KyungMoon Kim, SooSan Park, KeoChang Lee
  • Publication number: 20180261551
    Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Goo Lee, KyungMoon Kim, SooSan Park, KeoChang Lee
  • Patent number: 9859200
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 2, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: SooSan Park, KyuSang Kim, YeoChan Ko, KeoChang Lee, HeeJo Chi, HeeSoo Lee
  • Publication number: 20160190054
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.
    Type: Application
    Filed: July 6, 2015
    Publication date: June 30, 2016
    Inventors: SooSan Park, KyuSang Kim, YeoChan Ko, KeoChang Lee, HeeJo Chi, HeeSoo Lee
  • Patent number: 9184067
    Abstract: Semiconductor packages with multiple substrates can incorporate apertures or slots between devices to minimize or reduce formation of defects during a molding process. The apertures or slots can be formed adjacent a top substrate in alignment with removable regions adjacent a bottom substrate whereby the apertures or slots can facilitate outflow of materials from cavities between the substrates. The apertures or slots may subsequently be removed in conjunction with the removable regions during a singulation process thereby producing the desired semiconductor packages with improved device reliability and yield.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: KyungHwan Kim, DeokKyung Yang, SeongHun Mun, KeoChang Lee
  • Patent number: 9076802
    Abstract: Simultaneous semiconductor packages can be produced using a dual-sided film-assist molding process. The process involves using a film or membrane having opposing surfaces for receiving un-encapsulated semiconductor packages on both surfaces. A slot can be formed in the film or membrane to facilitate introduction and passage of the encapsulation therethrough such that upon removal of the film or membrane, increased throughput and productivity of the completed semiconductor packages can be carried out to achieve considerable cost savings.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: July 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: WonJun Ko, GwangTae Kim, KeoChang Lee