Patents by Inventor Keomyoung SHIN

Keomyoung SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12119347
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: October 15, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Publication number: 20230317725
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 5, 2023
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Patent number: 11710738
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Publication number: 20210313322
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Patent number: 11069681
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Publication number: 20200365586
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Application
    Filed: November 25, 2019
    Publication date: November 19, 2020
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Patent number: 9954061
    Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeongyun Lee, Kwang-Yong Yang, Keomyoung Shin, Jinwook Lee, Yongseok Lee
  • Publication number: 20170263711
    Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Jeongyun LEE, Kwang-Yong YANG, Keomyoung SHIN, Jinwook LEE, Yongseok LEE
  • Patent number: 9673279
    Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 6, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeongyun Lee, Kwang-Yong Yang, Keomyoung Shin, Jinwook Lee, Yongseok Lee
  • Publication number: 20170110542
    Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
    Type: Application
    Filed: July 12, 2016
    Publication date: April 20, 2017
    Inventors: Jeongyun LEE, Kwang-Yong YANG, Keomyoung SHIN, Jinwook LEE, Yongseok LEE