Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.

Abstract: A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a non-volatile memory interface circuit for transferring/receiving a signal to/from the internal circuit in synchronization with the first clock and transferring/receiving the signal to/from an external device in synchronization with a second clock that is asynchronous relative to the first clock.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: Provided are a semiconductor device and a data transmitting method thereof. The method includes transmitting data into a memory through at least one data line, scrambling the data corresponding to at least one mask data, and determining, using the at least one mask data, data integrity of the data transmitted through the at least one data line. The method may also include storing the data transmitted through the at least one data line in the memory according to a data integrity determination result.

Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.

Abstract: An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal, a second buffer for receiving data from the flash memory device in synchronization with the clock enable signal, a third buffer for receiving and outputting an output of the first buffer, and a latch circuit for latching an output of the second buffer in synchronization with output of the third buffer.

Abstract: A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.

Abstract: A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a non-volatile memory interface circuit for transferring/receiving a signal to/from the internal circuit in synchronization with the first clock and transferring/receiving the signal to/from an external device in synchronization with a second clock that is asynchronous relative to the first clock.

Abstract: Provided are a semiconductor device and a data transmitting method thereof. The method includes transmitting data into a memory through at least one data line, scrambling the data corresponding to at least one mask data, and determining, using the at least one mask data, data integrity of the data transmitted through the at least one data line. The method may also include storing the data transmitted through the at least one data line in the memory according to a data integrity determination result.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal a second buffer for receiving data from the flash memory device in synchronization with the clock enable signal, a third buffer for receiving and outputting an output of the first buffer, and a latch circuit for latching an output of the second buffer in synchronization with output of the third buffer.

Abstract: A card controller which may include a central processing unit; a booting memory for storing a plurality of command sets; a memory discriminator for extracting memory information from an added memory to transfer the extracted memory information to the central processing unit; and a memory controller configured to be set with the command set read from the booting memory based on a control of the central processing unit, so as to access the added memory may be provided.

Abstract: A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.