Patents by Inventor Keon Park

Keon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12253973
    Abstract: Smart information retrieval is provided via artificial intelligence. Content stored in documents in a database is accessed and contextual chunks of individual ones of the documents are identified, wherein the contextual chunks include portions of content stored in the individual ones of the documents. Embeddings associated with the contextual chunks are generated and stored in a vector database. A plurality of relationships are defined among at least some of the contextual chunks and generates relational embeddings using the plurality of identified relationships. The relational embeddings are stored in a database. A query is received for information associated with at least some of the content and an embedding representing the query is generated. The embedding representing the query is transmitted to at least one large language model, and a response including at least some of the contextual chunks is received. The response is transmitted to a device associated with the query.
    Type: Grant
    Filed: August 21, 2024
    Date of Patent: March 18, 2025
    Assignee: Morgan Stanley Services Group Inc.
    Inventors: Shailesh Gavankar, Afrid Mondal, Keon Park, Sanket Jain, Abhijit Naik
  • Patent number: 11994382
    Abstract: A system for automatically checking seat dimension accuracy for a vehicle may include a storage unit configured to store therein seat design data at a time of designing an actually produced seat and seat scan data obtained by scanning the actually produced seat, a controller configured to determine whether the actually produced seat has been produced to match predesigned dimensions using the seat design data and the seat scan data stored in the storage unit, and an output unit configured to automatically output a result of determination by the controller in a specific form. The system and a method for checking seat dimension accuracy for a vehicle can automatically check whether an actually produced seat has been accurately produced to match designed seat dimensions through automatic comparison of scan data of the actually produced seat with seat design data, and automatically generate a checking result report.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 28, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, TEXAS A&M UNIVERSITY-CORPUS CHRISTI
    Inventors: Baek Hee Lee, Min Hyuk Kwak, Yeong Sik Kim, Jang Woon Park, Byoung Keon Park
  • Publication number: 20230352041
    Abstract: The present invention relates to a speaker diarization technology, and more specifically to, end-to-end speaker diarization system and method through transformer learning having an auxiliary loss-based residual connection to separate speakers by dividing the speakers for time interval, wherein the end-to-end speaker diarization system and method using an auxiliary loss can differentiate and separate speakers through speaker labeling based on the transformer learning using an auxiliary loss even if speaker speeches overlap in a multi-speaker environment.
    Type: Application
    Filed: November 29, 2022
    Publication date: November 2, 2023
    Applicant: Gwangju Institute of Science and Technology
    Inventors: Dong Keon PARK, Hong Kook KIM, Ye Chan YU
  • Patent number: 10965934
    Abstract: A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Chan An, Min Chul Kim, Yon Jun Shin, Sang Heon Lee, Dae Keon Park, Woon Yong Jo
  • Publication number: 20200300620
    Abstract: A system for automatically checking seat dimension accuracy for a vehicle may include a storage unit configured to store therein seat design data at a time of designing an actually produced seat and seat scan data obtained by scanning the actually produced seat, a controller configured to determine whether the actually produced seat has been produced to match predesigned dimensions using the seat design data and the seat scan data stored in the storage unit, and an output unit configured to automatically output a result of determination by the controller in a specific form. The system and a method for checking seat dimension accuracy for a vehicle can automatically check whether an actually produced seat has been accurately produced to match designed seat dimensions through automatic comparison of scan data of the actually produced seat with seat design data, and automatically generate a checking result report.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 24, 2020
    Inventors: Baek Hee Lee, Min Hyuk Kwak, Yeong Sik Kim, Jang Woon Park, Byoung Keon Park
  • Patent number: 10193660
    Abstract: A header processing device includes an error detector, a controller, and a reallocator. The error detector detects an error in a header in a packet and outputs a header error detection result. The controller selects first and second information from the header based on information corresponding to a type of the header and the header error detection result. The reallocator merges the first and second information and generates a header with a common format different from a format of the header.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Yong Jo, Dae Keon Park, June Hee Lee
  • Patent number: 10147774
    Abstract: A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Dong-Hyun Lee, Jin-Wook Seo, Ki-Yong Lee
  • Patent number: 9947771
    Abstract: A method of fabricating a thin film transistor includes forming a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 17, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byoung-Keon Park
  • Publication number: 20180026748
    Abstract: A header processing device includes an error detector, a controller, and a reallocator. The error detector detects an error in a header in a packet and outputs a header error detection result. The controller selects first and second information from the header based on information corresponding to a type of the header and the header error detection result. The reallocator merges the first and second information and generates a header with a common format different from a format of the header.
    Type: Application
    Filed: February 9, 2017
    Publication date: January 25, 2018
    Inventors: Woon Yong JO, Dae Keon PARK, June Hee LEE
  • Publication number: 20170201746
    Abstract: A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 13, 2017
    Inventors: HYO CHAN AN, MIN CHUL KIM, YON JUN SHIN, SANG HEON LEE, DAE KEON PARK, WOON YONG JO
  • Patent number: 9576797
    Abstract: A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Lee, Ki-Yong Lee, Jin-Wook Seo, Tae-Hoon Yang, Yun-Mo Chung, Byoung-Keon Park, Kil-Won Lee, Jong-Ryuk Park, Bo-Kyung Choi, Byung-Soo So
  • Patent number: 9406730
    Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 2, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Yun-Mo Chung, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee, Min-Jae Jeong, Yong-Duck Son, Byung-Soo So, Seung-Kyu Park, Dong-Hyun Lee, Kil-Won Lee, Jae-Wan Jung
  • Patent number: 9142405
    Abstract: A thin film transistor including a first polycrystalline semiconductor layer disposed on a substrate, a second polycrystalline semiconductor layer disposed on the first polycrystalline semiconductor layer, and metal catalysts configured to adjoin the first polycrystalline semiconductor layer and spaced apart from one another at specific intervals.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 22, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Duck Son, Ki-Yong Lee, Jin-Wook Seo, Min-Jae Jeong, Byung-Soo So, Seung-Kyu Park, Kil-Won Lee, Yun-Mo Chung, Byoung-Keon Park, Dong-Hyun Lee, Jong-Ryuk Park, Tak-Young Lee, Jae-Wan Jung
  • Publication number: 20150263135
    Abstract: A method of fabricating a thin film transistor includes forming a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.
    Type: Application
    Filed: June 3, 2015
    Publication date: September 17, 2015
    Inventor: Byoung-Keon PARK
  • Publication number: 20150255282
    Abstract: A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Dong-Hyun LEE, Ki-Yong LEE, Jin-Wook SEO, Tae-Hoon YANG, Yun-Mo CHUNG, Byoung-Keon PARK, Kil-Won LEE, Jong-Ryuk PARK, Bo-Kyung CHOI, Byung-Soo SO
  • Patent number: 9117798
    Abstract: A thin film transistor, a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same. The thin film transistor includes a substrate; a semiconductor layer disposed on the substrate and including a channel region; source/drain regions including ions and an offset region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; a first insulating layer disposed on the gate electrode; a second insulating layer disposed on the first insulating layer; and source/drain electrodes disposed on the second insulating layer, and electrically connected to the source/drain regions of the semiconductor layer, respectively. The sum of thicknesses of the gate insulating layer and the first insulating layer that are on the source/drain regions is less than the vertical dispersion depth of the ions included in the source/drain regions.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 25, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Ki-Yong Lee, Hyun-Gue Kim, Maxim Lisachenko, Dong-Hyun Lee, Kil-Won Lee, Jong-Ryuk Park, Bo-Kyung Choi
  • Patent number: 9070717
    Abstract: A method of fabricating an organic light emitting diode (OLED) display device having a thin film transistor including a polysilicon layer. The method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 30, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Lee, Ki-Yong Lee, Jin-Wook Seo, Tae-Hoon Yang, Yun-Mo Chung, Byoung-Keon Park, Kil-Won Lee, Jong-Ryuk Park, Bo-Kyung Choi, Byung-Soo So
  • Patent number: 9070716
    Abstract: A thin film transistor including a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: June 30, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byoung-Keon Park
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9034156
    Abstract: Provided is a sputtering apparatus which deposits a metal catalyst on an amorphous silicon layer at an extremely low concentration in order to crystallize amorphous silicon, and particularly minimizes non-uniformity of the metal catalyst caused by a pre-sputtering process without reducing process efficiency. This sputtering apparatus improves the uniformity of the metal catalyst deposited on the amorphous silicon layer at an extremely low concentration. The sputtering apparatus includes a process chamber having first and second regions, a metal target located inside the process chamber, a target transfer unit moving the metal target and having a first shield for controlling a traveling direction of a metal catalyst discharged from the metal target, and a substrate holder disposed in the second region to be capable of facing the metal target.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park, Yun-Mo Chung, Dong-Hyun Lee, Kil-Won Lee, Jae-Wan Jung, Jong-Ryuk Park, Bo-Kyung Choi, Won-Bong Baek, Byung-Soo So, Jong-Won Hong, Min-Jae Jeong, Heung-Yeol Na, Ivan Maidanchuk, Eu-Gene Kang, Seok-Rak Chang