Patents by Inventor Keon-Yong Cheon
Keon-Yong Cheon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230122379Abstract: A semiconductor device includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern, a gate structure on the lower pattern and having a gate electrode and a gate insulating film that surround each of the sheet patterns, a gate capping pattern on the gate structure, a gate etching stop pattern between the gate capping pattern and the gate structure, a gate spacer along a sidewall of the gate capping pattern, a source/drain pattern on the gate structure, a gate contact through the gate capping pattern and connected to the gate electrode, upper surfaces of the gate contact and gate spacer being coplanar, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern.Type: ApplicationFiled: August 2, 2022Publication date: April 20, 2023Inventors: Shin Cheol MIN, Keon Yong CHEON, Myung Dong KO, Yong Hee PARK, Sang Hyeon LEE, Dong Won KIM, Woo Seung SHIN, Hyung Suk LEE
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Publication number: 20230019860Abstract: A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.Type: ApplicationFiled: April 12, 2022Publication date: January 19, 2023Inventors: Myung-Dong KO, Keon Yong CHEON, Dong Won KIM, Hyun Suk KIM, Sang Hyeon LEE, Hyung Suk LEE
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Patent number: 10957795Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.Type: GrantFiled: April 10, 2020Date of Patent: March 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Hee Park, Myung Gil Kang, Young-Seok Song, Keon Yong Cheon
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Patent number: 10916534Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.Type: GrantFiled: April 26, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Seok Ha, Kyoung-Mi Park, Hyun-Seung Song, Keon Yong Cheon, Dae Won Ha
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Publication number: 20200243682Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Yong Hee PARK, Myung Gil KANG, Young-Seok SONG, Keon Yong CHEON
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Patent number: 10665702Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.Type: GrantFiled: October 4, 2018Date of Patent: May 26, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Gil Kang, Ill Seo Kang, Yong Hee Park, Sang Hoon Baek, Keon Yong Cheon
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Patent number: 10622476Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.Type: GrantFiled: September 12, 2018Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Hee Park, Myung Gil Kang, Young-Seok Song, Keon Yong Cheon
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Publication number: 20200027870Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.Type: ApplicationFiled: April 26, 2019Publication date: January 23, 2020Inventors: Seung Seok HA, Kyoung-Mi PARK, Hyun-Seung SONG, Keon Yong CHEON, Dae Won HA
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Publication number: 20190198648Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.Type: ApplicationFiled: October 4, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Myung Gil KANG, Ill Seo KANG, Yong Hee PARK, Sang Hoon BAEK, Keon Yong CHEON
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Publication number: 20190198669Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.Type: ApplicationFiled: September 12, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Yong Hee PARK, Myung Gil KANG, Young-Seok SONG, Keon Yong CHEON
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Patent number: 9905645Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.Type: GrantFiled: September 2, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Gil Kang, Seung Han Park, Yong Hee Park, Sang Hoon Baek, Sang Woo Lee, Keon Yong Cheon, Sung Man Whang
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Publication number: 20170345897Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.Type: ApplicationFiled: September 2, 2016Publication date: November 30, 2017Inventors: Myung Gil KANG, Seung Han PARK, Yong Hee PARK, Sang Hoon BAEK, Sang Woo LEE, Keon Yong CHEON, Sung Man WHANG
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Publication number: 20170033107Abstract: A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.Type: ApplicationFiled: May 20, 2016Publication date: February 2, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Byoung Hak HONG, Sungil Park, Toshinori Fukai, Shigenobu Maeda, Sada-aki Masuoka, Sanghyun Lee, Keon Yong Cheon, Hock-Chun Chin
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Patent number: 9461132Abstract: Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the gate patterns have different gate electrode metals from each other or different gate electrode metal thicknesses from each other.Type: GrantFiled: October 10, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keon-Yong Cheon, Il-Ryong Kim, Dong-Won Kim
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Publication number: 20150263004Abstract: Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the gate patterns have different gate electrode metals from each other or different gate electrode metal thicknesses from each other.Type: ApplicationFiled: October 10, 2014Publication date: September 17, 2015Inventors: KEON-YONG CHEON, IL-RYONG KIM, DONG-WON KIM
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Publication number: 20150097250Abstract: Provided is a semiconductor device, which includes a first fin on a substrate, a first gate insulating layer including a first trench disposed on the first fin, a first work function adjusting layer in the first trench, a first barrier layer covering a top surface of the first work function adjusting layer; and an interlayer insulating layer on the first barrier layer.Type: ApplicationFiled: July 10, 2014Publication date: April 9, 2015Inventors: Keon-Yong CHEON, Jun-suk CHOI, Han-Su OH, Yoshinao HARADA
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Patent number: 8816412Abstract: An image sensor having a light receiving region and an optical black region includes a semiconductor substrate, an interconnection disposed on the semiconductor substrate and extending along an interface between the light receiving region and the optical black region, and via plugs disposed between the interconnection and the semiconductor substrate and serving as light shielding members at the interface. The via plugs are arranged in a zigzagging pattern along the interface.Type: GrantFiled: June 8, 2011Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Keon Yong Cheon, Jong-Won Choi, Sung-Hyun Yoon
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Patent number: 8753945Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.Type: GrantFiled: November 28, 2012Date of Patent: June 17, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Keon-Yong Cheon, Dong-Won Kim, Sung-Man Lim, Sadaaki Masuoka, Yaoqi Dong
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Publication number: 20130252393Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.Type: ApplicationFiled: November 28, 2012Publication date: September 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keon-Yong CHEON, Dong-Won KIM, Sung-Man LIM, Sadaaki MASUOKA, Yaoqi DONG
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Patent number: 8420432Abstract: Provided is a method of forming a semiconductor device. The method includes forming an insulating film on a semiconductor substrate, a conductive film on the insulating film, and a first structure and a second structure on the conductive film. The semiconductor substrate has first and second regions. The first and second structures are formed on the first and second regions, respectively. An impurity diffused region is formed in the semiconductor substrate using the first structure as a mask. The impurity diffused region overlaps the first structure. A portion of the first structure, and the conductive film are etched to respectively form a gate structure and a capacitor structure on the first and second regions.Type: GrantFiled: September 8, 2011Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Choi, Jun-Seok Yang, Keon-Yong Cheon, Sung-Hyun Yoon