Patents by Inventor Keong Hong Oh

Keong Hong Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits And Methods For Multi-Layered Networks
    Publication number: 20240031308
    Abstract: An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: Rahul Pal, Ashish Gupta, Keong Hong Oh, Gia Thuyet Ngo, Vikrant Kapila, Ankita Roy
  • Clock synchronization in multi-die field programmable gate array devices
    Patent number: 10530367
    Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
  • CLOCK SYNCHRONIZATION IN MULTI-DIE FIELD PROGRAMMABLE GATE ARRAY DEVICES
    Publication number: 20190140647
    Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
  • Multi-layer distributed network
    Patent number: 9430433
    Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 30, 2016
    Assignee: Altera Corporation
    Inventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Loh, Chooi Pei Lim
  • Multi-layer distributed network
    Patent number: 8683405
    Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: March 25, 2014
    Assignee: Altera Corporation
    Inventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Lob, Chooi Pei Lim
  • MULTI-LAYER DISTRIBUTED NETWORK
    Publication number: 20120169362
    Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Inventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Lob, Chooi Pei Lim
  • Multi-layer distributed network
    Patent number: 8166429
    Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 24, 2012
    Assignee: Altera Corporation
    Inventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Loh, Chooi Pei Lim