Abstract: A data bus includes: a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions, and output the selected at least one transaction; and a memory data path including at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus.

Abstract: A data bus includes: a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions, and output the selected at least one transaction; and a memory data path including at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus.

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A method for controlling a memory operation includes determining a number of commands for each memory address based on information of requests stored in an interface buffer and a scheduler buffer, determining a control state of the memory operation according to a command type with a largest number of commands, and determining types of a request transmitted to the scheduler buffer from the interface buffer and a request output from the scheduler buffer according to a control state of the memory operation. Other embodiments including an apparatus for controlling a memory are also disclosed.

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A method for controlling a memory operation includes determining a number of commands for each memory address based on information of requests stored in an interface buffer and a scheduler buffer, determining a control state of the memory operation according to a command type with a largest number of commands, and determining types of a request transmitted to the scheduler buffer from the interface buffer and a request output from the scheduler buffer according to a control state of the memory operation. Other embodiments including an apparatus for controlling a memory are also disclosed.