Abstract: Provided are a face image processing method and apparatus, an image device, and a storage medium. The face image processing method includes: acquiring first-key-point information of a first face image; performing position transformation on the first-key-point information to obtain second-key-point information conforming to a second facial geometric attribute, the second facial geometric attribute being different from a first facial geometric attribute corresponding to the first-key-point information; and performing facial texture coding processing by utilizing a neural network and the second-key-point information to obtain a second face image.

Abstract: An electrode plate, an electrode assembly, and a secondary battery are provided. The electrode plate includes a current collector, an active material layer arranged on one surface of the current collector, and an electrical connection member electrically connected to the current collector. The active material layer is arranged on a main body portion of the current collector, the electrical connection member and the current collector are connected to each other by welding at an edge of the current collector, the welding connection region is referred to as a transfer welding region, and the current collector includes a support layer and an electrically conductive layer arranged on one surface of the support layer. The electrode plate further includes a first insulation layer arranged on a further surface of the current collector and covering at least the entirety of the transfer welding region when viewed in a thickness direction of the electrode plate.

Abstract: The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.

Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.

Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution.

Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution.

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Abstract: Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.

Abstract: Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.

Abstract: T-DNA tagging with a promoterless ?-glucuronidase (GUS) gene generated transgenic Nicotiana tabacum plants that expressed GUS activity either only in developing seed coats, or constitutively. Cloning and deletion analysis of the GUS fusion revealed that the promoter responsible for seed coat specificity was located in the plant DNA proximal to the GUS gene. Analysis of the region demonstrated that the seed coat-specificity of GUS expression in this transgenic plant resulted from T-DNA insertion next to a cryptic promoter. This promoter is useful in controlling the expression of genes to the developing seed coat in plant seeds. Similarly, cloning and characterization of the cryptic constitutive promoter revealed the occurrence of several cryptic regulatory regions. These regions include promoter, negative regulatory elements, transcriptional enhancers, core promoter regions, and translational enhancers and other regulatory elements.