Patents by Inventor Kermin E. ChoFleming, JR.

Kermin E. ChoFleming, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230367640
    Abstract: An offload analyzer analyzes a program for porting to a heterogenous computing system by identifying code objects for offloading to an accelerator. Runtime metrics generated by executing the program on a host processor unit are provided to an accelerator model that models the performance of the accelerator and generates estimated accelerator metrics for the program. A code object offload selector selects code objects for offloading based on whether estimated accelerated times of the code objects, which comprise estimated accelerator times and offload overhead times, are better than their host processor unit execution times. The code object offload selector selects additional code objects for offloading using a dynamic-programming-like performance estimation approach that performs a bottom-up traversal of a call tree. A heterogeneous version of the program can be generated for execution on the heterogeneous computing system.
    Type: Application
    Filed: April 23, 2021
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Kermin E. ChoFleming, Jr., Egor A. Kazachkov, Daya Shanker Khudia, Zakhar A. Matveev, Sergey U. Kokljuev, Fabrizio Petrini, Dmitry S. Petrov, Swapna Raj
  • Patent number: 11693633
    Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 4, 2023
    Assignee: INTEL CORPORATION
    Inventors: Kermin E. ChoFleming, Jr., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan
  • Publication number: 20210365248
    Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
    Type: Application
    Filed: June 7, 2021
    Publication date: November 25, 2021
    Inventors: Kermin E. ChoFleming, JR., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan
  • Patent number: 11029927
    Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kermin E. ChoFleming, Jr., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan
  • Patent number: 10965536
    Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Kermin E. ChoFleming, Jr., Jesmin Jahan Tithi, Suresh Srinivasan, Mahesh A. Iyer
  • Publication number: 20190229996
    Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.
    Type: Application
    Filed: March 30, 2019
    Publication date: July 25, 2019
    Inventors: Kermin E. ChoFleming, JR., Jesmin Jahan Tithi, Suresh Srinivasan, Mahesh A. Iyer
  • Publication number: 20190227777
    Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
    Type: Application
    Filed: March 30, 2019
    Publication date: July 25, 2019
    Inventors: Kermin E. ChoFleming, JR., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan