Abstract: An integrated circuit includes a memory interface, coupled to a memory to store data corresponding to instructions, and an operations queue to buffer memory operations corresponding to the instructions. The integrated circuit may include acceleration hardware to execute a sub-program corresponding to the instructions. A set of input queues may include an address queue to receive, from the acceleration hardware, an address of the memory associated with a second memory operation of the memory operations, and a dependency queue to receive, from the acceleration hardware, a dependency token associated with the address. The dependency token indicates a dependency on data generated by a first memory operation of the memory operations. A scheduler circuit may schedule issuance of the second memory operation to the memory in response to the dependency queue receiving the dependency token and the address queue receiving the address.

Abstract: An integrated circuit includes a processor to execute instructions and to interact with memory, and acceleration hardware, to execute a sub-program corresponding to instructions. A set of input queues includes a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation and a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory. The set of input queues also includes a completion queue to buffer response data for a load operation. A disambiguator circuit, coupled to the set of input queues and the memory, is to, responsive to determining the load operation, which succeeds the store operation, has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.

Abstract: An integrated circuit includes a processor to execute instructions and to interact with memory, and acceleration hardware, to execute a sub-program corresponding to instructions. A set of input queues includes a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation and a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory. The set of input queues also includes a completion queue to buffer response data for a load operation. A disambiguator circuit, coupled to the set of input queues and the memory, is to, responsive to determining the load operation, which succeeds the store operation, has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.

Abstract: An integrated circuit includes a memory interface, coupled to a memory to store data corresponding to instructions, and an operations queue to buffer memory operations corresponding to the instructions. The integrated circuit may include acceleration hardware to execute a sub-program corresponding to the instructions. A set of input queues may include an address queue to receive, from the acceleration hardware, an address of the memory associated with a second memory operation of the memory operations, and a dependency queue to receive, from the acceleration hardware, a dependency token associated with the address. The dependency token indicates a dependency on data generated by a first memory operation of the memory operations. A scheduler circuit may schedule issuance of the second memory operation to the memory in response to the dependency queue receiving the dependency token and the address queue receiving the address.

Abstract: A system and techniques for decoding a message received over a communication channel comprises a receiver for receiving an encoded message. A sorting module is configured to organize candidate messages into a number of bins, sort the candidate messages within each bin, and output a group of candidate messages, the group comprising a number of most likely candidate messages from each message bin. A traceback module is configured to receive the most likely candidate message, and to walk through the tree of candidate messages to generate a decoded message.

Abstract: A system and techniques for decoding a message received over a communication channel comprises a receiver for receiving an encoded message. A sorting module is configured to organize candidate messages into a number of bins, sort the candidate messages within each bin, and output a group of candidate messages, the group comprising a number of most likely candidate messages from each message bin. A traceback module is configured to receive the most likely candidate message, and to walk through the tree of candidate messages to generate a decoded message.

Abstract: A system and techniques for decoding a message received over a communication channel comprises a receiver for receiving an encoded message. A sorting module is configured to organize candidate messages into a number of bins, sort the candidate messages within each bin, and output a group of candidate messages, the group comprising a number of most likely candidate messages from each message bin. A traceback module is configured to receive the most likely candidate message, and to walk through the tree of candidate messages to generate a decoded message.

Abstract: A system and techniques for decoding a message received over a communication channel comprises a receiver for receiving an encoded message. A sorting module is configured to organize candidate messages into a number of bins, sort the candidate messages within each bin., and output a group of candidate messages, the group comprising a number of most likely candidate messages from each message bin.