Patents by Inventor Kern W. Wong

Kern W. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7454640
    Abstract: A system and method is disclosed that provides a thermal shutdown circuit that generates a plurality of temperature warning flag signals. Each temperature warning flag signal represents a different temperature. The thermal shutdown circuit comprises a plurality of inverter circuits in which each inverter circuit has a different temperature turn-on threshold. A temperature to binary code converter receives the temperature warning flag signals from the inverter circuits and generates a plurality of binary coded signals that represent a temperature that is detected by the thermal shutdown circuit. A host controller unit uses the temperature information from the binary coded signals to shut down subsystems in advance of an abrupt thermal shutdown of a system.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: November 18, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Kern W. Wong
  • Patent number: 7408335
    Abstract: A band-gap reference circuit comprising a first current source for generating a first reference current and a first circuit branch for receiving part of the first reference current. The first circuit branch comprises a first resistor having a positive temperature coefficient in series with a base-emitter junction of a first PNP diode having a negative temperature coefficient. An emitter current of the first PNP diode develops a first combined voltage across the first resistor and the base-emitter junction. A comparison circuit compares the first combined voltage to a base-emitter voltage of a second PNP diode and adjusts a band-gap reference voltage. A correction current generating circuit injects a correction current into an emitter of the second PNP diode that at least partially offsets a non-linear drop-off in the band-gap reference voltage caused by the second PNP diode as temperature increases.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 5, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Kern W. Wong, Jane Xin-Leblanc
  • Patent number: 7274114
    Abstract: A tracking and control method and circuit for use in a power management unit integrated circuit (PMUIC) that enables multiple voltage regulator outputs to maintain a same voltage or a ratiometric relation to a reference voltage source. When the reference voltage source is powered down or falls below a prescribed level, the tracking power supplies are automatically switched to their internal bandgap reference voltage. Accordingly, outputs of the tracking power supplies are prevented from introducing large transient excursions that might result in malfunctions in the circuitry of the load such as latch-ups. Ratiometric tracking further provides coordinated preservation of logic interface levels, and reduces leakage current.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: September 25, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Kern W. Wong
  • Patent number: 7215103
    Abstract: A method and circuit for automatically lowering a quiescent current at a predetermined threshold. A compact and low power current comparator is employed to detect the power consumption conditions, and issues a control signal to lower current consumption within a power management circuit. By dynamically resizing bias device geometries, a minimum quiescent current of an electronic device may be further reduced. Moreover, the control signal may also be used to engage modification of circuit dynamics to improve circuit performance and mitigate a response profile during recovery from a low power operation.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: May 8, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Kern W. Wong, Kenneth Robert Marasco
  • Patent number: 7023227
    Abstract: There is disclosed apparatus for socketing and testing integrated circuits, particularly RF and high-frequency integrated circuits in high density and fine pitch packages, and methods of operating the same. An exemplary apparatus includes an air machine and a housing. The housing includes a universal printed circuit board that is operable to receive a device under test, a controller that is operable to control testing of the received device under test, and a power supply. The housing and the air machine are associable to form an at least substantially air-tight chamber ensconcing the received device under test.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Kern W. Wong
  • Patent number: 6724176
    Abstract: A band-gap reference circuit comprising a first current source for generating a first reference current and a first circuit branch for receiving part of the first reference current. The first circuit branch comprises a first resistor having a positive temperature coefficient in series with a base-emitter junction of a first PNP diode having a negative temperature coefficient. An emitter current of the first PNP diode develops a first combined voltage across the first resistor and the base-emitter junction. A comparison circuit compares the first combined voltage to a base-emitter voltage of a second PNP diode and adjusts a band-gap reference voltage. A correction current generating circuit injects a correction current into an emitter of the second PNP diode that at least partially offsets a non-linear drop-off in the band-gap reference voltage caused by the second PNP diode as temperature increases.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: April 20, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Kern W. Wong, Jane Xin-Leblanc
  • Patent number: 6541948
    Abstract: A voltage regulator formed on an integrated circuit is provided that includes an amplifier and a feedback circuit. The amplifier is operable to receive a reference voltage and a feedback voltage. The amplifier is also operable to generate a regulated output voltage based on the reference voltage and the feedback voltage. The feedback circuit, which is coupled to the amplifier, is operable to generate the feedback voltage. The feedback circuit includes an inductor-capacitor network. The inductor-capacitor network is operable to remove high frequencies from the output voltage.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: April 1, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Kern W. Wong
  • Patent number: 4754216
    Abstract: An ultra-compact window margin performance test apparatus for PLL data synchronizer integrated circuits includes self-contained programmable digital pattern generator, a moveable test bit generator capable of continuously adjustable bit delay time and bit pulse width for up to 25 megabit per second data rate operation. The apparatus also includes two independent oscillators for the 2F reference clock and for general system timing, a selectable Early/Late strobe or window center adjustment, and monitoring signals directly output to oscilloscope and ratio counter for accurate measurement of window margin data. The apparatus may be used to evaluate the bit tolerance merit of the PLL DUT. It may also be used as a design tool for basic PLL analysis and loop filter design optimization works. Additionally, the apparatus is a standardized correlation fixture suitable for use in quality assurance and manufacturing environments.
    Type: Grant
    Filed: September 3, 1987
    Date of Patent: June 28, 1988
    Assignee: National Semiconductor Corporation
    Inventor: Kern W. Wong