Abstract: The present disclosure includes mapping redundant addresses in a multi-node system by receiving a first address and a first node ID, determining a first address type representing an address redundancy level for the first address, determining a first node ID type representing a node ID redundancy level for the first node ID, and determining a second address and a second node ID based on the first address type and the first node ID type.

Abstract: The present disclosure includes mapping redundant addresses in a multi-node system by receiving a first address and a first node ID, determining a first address type representing an address redundancy level for the first address, determining a first node ID type representing a node ID redundancy level for the first node ID, and determining a second address and a second node ID based on the first address type and the first node ID type.

Abstract: A method and elastic buffer circuit are provided for implementing low power, single master-slave elastic buffers in a network chip design to provide a continuous stream of data to multiple sinks from multiple sources, and a design structure on which the subject circuit resides. An elastic buffer only uses a single master-slave register. The circuit includes a finite state machine, and a latch control block (LCB) to implement the single master-slave elastic buffer removing all ½ cycle paths between buffer locations enabling usage of the single master-slave register.

Abstract: A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.

Abstract: In a first aspect, a method for maintaining control structure coherency is provided. The method includes the steps of (1) writing a pointer to a control structure in a hardware update list while one or more portions of the control structure are accessed by hardware during a hardware update operation; and (2) delaying a software access to one or more portions of the control structure during a software update operation while the pointer to the control structure is on the hardware update list. Numerous other aspects are provided.