Patents by Inventor Kerry JOSEPH
Kerry JOSEPH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250031580Abstract: A method of manufacturing a magnetoresistive device may comprise providing a magnetoresistive structure comprising a bottom electrode, a magnetoresistive stack, and a top electrode. The method may include removing at least a portion of the top electrode using a first etch, where the first etch is performed in the presence of a first gas mixture. Methods of manufacturing the magnetoresistive device may include removing at least a portion of the magnetoresistive stack and the bottom electrode using a second etch, wherein the second etch is performed in the presence of a second gas mixture. The first and second gas mixture may comprise a hydrocarbon including a carbon-carbon double bond or a carbon-carbon triple bond.Type: ApplicationFiled: July 18, 2024Publication date: January 23, 2025Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, SHIMON, Sanjeev AGGARWAL
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Publication number: 20240420796Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.Type: ApplicationFiled: June 11, 2024Publication date: December 19, 2024Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Jacob T. WILLIAMS, Michael A. SADD, Kerry Joseph NAGEL, Sumio IKEGAWA, Frederick B. MANCOFF, Sanjeev AGGARWAL
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Publication number: 20240412520Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.Type: ApplicationFiled: August 14, 2024Publication date: December 12, 2024Applicant: Intellective Ai, Inc.Inventors: Wesley Kenneth COBB, Ming-Jung SEOW, Gang XU, Kishor Adinath SAITWAL, Anthony AKINS, Kerry JOSEPH, Dennis G. URECH
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Patent number: 12094212Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.Type: GrantFiled: June 23, 2023Date of Patent: September 17, 2024Assignee: Intellective Ai, Inc.Inventors: Wesley Kenneth Cobb, Ming-Jung Seow, Gang Xu, Kishor Adinath Saitwal, Anthony Akins, Kerry Joseph, Dennis G. Urech
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Patent number: 12075630Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.Type: GrantFiled: October 11, 2022Date of Patent: August 27, 2024Assignee: Everspin Technologies, Inc.Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande
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Patent number: 12063865Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.Type: GrantFiled: August 10, 2020Date of Patent: August 13, 2024Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
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Publication number: 20240114802Abstract: A magnetoresistive stack may include a fixed magnetic region, where the fixed magnetic region may include a reference layer, an interfacial layer disposed above the reference layer, an intermediate layer disposed above the interfacial layer, and a free magnetic region disposed above the intermediate layer. The interfacial layer may include cobalt (Co).Type: ApplicationFiled: October 2, 2023Publication date: April 4, 2024Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Kerry Joseph NAGEL
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Publication number: 20240107891Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, Sarin A. DESHPANDE, Kerry Joseph NAGEL
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Publication number: 20240049607Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.Type: ApplicationFiled: October 10, 2023Publication date: February 8, 2024Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
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Publication number: 20230419669Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.Type: ApplicationFiled: June 23, 2023Publication date: December 28, 2023Applicant: Intellective Ai, Inc.Inventors: Wesley Kenneth COBB, Ming-Jung SEOW, Gang XU, Kishor Adinath SAITWAL, Anthony AKINS, Kerry JOSEPH, Dennis G. URECH
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Publication number: 20230403943Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: ApplicationFiled: August 25, 2023Publication date: December 14, 2023Applicant: Everspin Technologies, Inc.Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
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Patent number: 11778919Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: GrantFiled: October 26, 2021Date of Patent: October 3, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
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Patent number: 11727689Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.Type: GrantFiled: July 16, 2021Date of Patent: August 15, 2023Assignee: Intellective Ai, Inc.Inventors: Wesley Kenneth Cobb, Ming-Jung Seow, Gang Xu, Kishor Adinath Saitwal, Anthony Akins, Kerry Joseph, Dennis G. Urech
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Publication number: 20230225217Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Kenneth SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
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Patent number: 11631806Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: GrantFiled: May 11, 2021Date of Patent: April 18, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
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Publication number: 20230100514Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.Type: ApplicationFiled: October 11, 2022Publication date: March 30, 2023Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Thomas ANDRE, Sarin A. DESHPANDE
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Publication number: 20230053632Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.Type: ApplicationFiled: October 11, 2022Publication date: February 23, 2023Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, SHIMON, Kerry Joseph NAGEL
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Patent number: 11502247Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.Type: GrantFiled: December 28, 2020Date of Patent: November 15, 2022Assignee: Everspin Technologies, Inc.Inventors: Sanjeev Aggarwal, Shimon, Kerry Joseph Nagel
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Patent number: 11482570Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.Type: GrantFiled: December 28, 2020Date of Patent: October 25, 2022Assignee: Everspin Technologies, Inc.Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande
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Publication number: 20220209104Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, SHIMON, Kerry Joseph NAGEL