Patents by Inventor Kerry JOSEPH

Kerry JOSEPH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120590
    Abstract: This disclosure relates generally to an apparatus for organizing battery cells. The apparatus includes a block including: sleeves forming chambers, a first sheet configured to locate the sleeves, and a foam structure surrounding the sleeves. Each chamber is configured to accommodate a battery cell. The block is configured to: organize the battery cells into battery cell groups, separate each battery cell group from its adjacent battery cell groups using a thermally insulating material, and prevent gas from entering into each battery cell group from its adjacent battery cell groups. Each battery cell group includes a plurality of the battery cells, each of the battery cells in the battery cell group is adjacent to at least another of the battery cells in the battery cell group. Each battery cell group is adjacent to at least another battery cell group.
    Type: Application
    Filed: April 7, 2023
    Publication date: April 11, 2024
    Applicant: Archer Aviation, Inc.
    Inventors: Alex CLARABUT, Likhith MADAMANCHI, Alex Ho YANG, Ryan Joseph CHERNIAK, Kerry MANNING
  • Publication number: 20240114802
    Abstract: A magnetoresistive stack may include a fixed magnetic region, where the fixed magnetic region may include a reference layer, an interfacial layer disposed above the reference layer, an intermediate layer disposed above the interfacial layer, and a free magnetic region disposed above the intermediate layer. The interfacial layer may include cobalt (Co).
    Type: Application
    Filed: October 2, 2023
    Publication date: April 4, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Jijun SUN, Kerry Joseph NAGEL
  • Publication number: 20240107891
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Sarin A. DESHPANDE, Kerry Joseph NAGEL
  • Publication number: 20240049607
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 8, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
  • Publication number: 20230419669
    Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 28, 2023
    Applicant: Intellective Ai, Inc.
    Inventors: Wesley Kenneth COBB, Ming-Jung SEOW, Gang XU, Kishor Adinath SAITWAL, Anthony AKINS, Kerry JOSEPH, Dennis G. URECH
  • Publication number: 20230403943
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 14, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
  • Patent number: 11778919
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 3, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 11727689
    Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 15, 2023
    Assignee: Intellective Ai, Inc.
    Inventors: Wesley Kenneth Cobb, Ming-Jung Seow, Gang Xu, Kishor Adinath Saitwal, Anthony Akins, Kerry Joseph, Dennis G. Urech
  • Publication number: 20230225217
    Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 13, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Kenneth SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
  • Patent number: 11631806
    Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: April 18, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Publication number: 20230100514
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Application
    Filed: October 11, 2022
    Publication date: March 30, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Thomas ANDRE, Sarin A. DESHPANDE
  • Publication number: 20230053632
    Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 23, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, SHIMON, Kerry Joseph NAGEL
  • Patent number: 11502247
    Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 15, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Shimon, Kerry Joseph Nagel
  • Patent number: 11482570
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 25, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande
  • Publication number: 20220209104
    Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, SHIMON, Kerry Joseph NAGEL
  • Patent number: 11335728
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 17, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande
  • Publication number: 20220149271
    Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 12, 2022
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry Joseph NAGEL
  • Publication number: 20220045269
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 10, 2022
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
  • Patent number: 11211553
    Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 28, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Joseph Nagel
  • Publication number: 20210398418
    Abstract: Alert directives and focused alert directives allow a user to provide feedback to a behavioral recognition system to always or never publish an alert for certain events. Such an approach bypasses the normal publication methods of the behavioral recognition system yet does not obstruct the system's learning procedures.
    Type: Application
    Filed: July 16, 2021
    Publication date: December 23, 2021
    Applicant: Intellective Ai, Inc.
    Inventors: Wesley Kenneth COBB, Ming-Jung SEOW, Gang XU, Kishor Adinath SAITWAL, Anthony AKINS, Kerry JOSEPH, Dennis G. URECH