Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A programmable crypto processing system (10) includes several processing resources (14, 16, 26) implemented on a single ULSI die. The processing system is both key and algorithm agile allowing for simultaneous execution of a variety of cryptographic programs through the use of background staging of the next program and context (key and state) during execution of a current program. The programmable crypto processing system includes a programmable crypto processor (17) for processing data units in accordance with a channel program, a crypto controller (11) for identifying a channel program, two interface processors (13, 15) for asynchronously receiving and transferring data units from and from an external host. Data units identify a particular channel program, and are processed in a selected processing engine in accordance the identified channel program.

Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Abstract: A configurable cryptographic processing engine (100) provides high performance cryptographic processing support for symmetric combiner type cryptographic algorithms. As many as two independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A 3-stage instruction pipeline, dynamically configurable cryptographic co-processor (550), and 32-bit RISC based architecture support high performance cryptographic processing performance on the order of 60 Mbps aggregate throughput.

Abstract: A process (20) is presented for determining the total routine energy (78) consumed by a processor (22) during the execution of a code routine (36). This total routine energy (78) is computed by determining the operation energy (76) consumed in the execution of each operating instruction (38) within the code routine (36). The operation energy (76) for each operating instruction (38) is computed by determining the average operation power (74) consumed during the execution of the operating instruction (38). The average operation power (74) for each operating instruction (38) is determined by determining an instruction power (90) and a summed-action power (92) for that operating instruction (38). The summed-action power (92) is the sum of action powers (96) computed through the use of an action formula (100) for each internal action (88) performed by the processor (22) in response to the operating instruction (38).