Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.

Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.

Abstract: A memory management interface is provided to synchronize the operation of two disparate operating systems (OSes) that are executing on the same data processing platform. In one embodiment, the first operating system is a legacy OS of the type that is generally associated with an enterprise-level data processing system such as a mainframe. In contrast, the second OS is of a type designed to execute on commodity hardware such as personal computers. The first OS communicates with the second OS via a control logic interface to establish its execution environment, and to perform memory management functions. This interface supports a two-phase boot process that ensures that all memory allocated to the first OS can be released if an error occurs that affects operations of the first OS. This prevents the development of memory leaks.

Abstract: The present invention provides methods and apparatus for authorizing a temporary or permanent increase in the performance of a data processing system while providing little or no down time. This is accomplished by including extra or additional computer resources in the data processing system when, for example, it is provided to the customer. However, only those resources required to achieve the performance level purchased by the customer are enabled for use during normal operation. To temporarily or permanently increase the performance level of the data processing system, the customer purchases an authorization key. When the customer desires increased performance, the authorization key is registered on the data processing system, which enables the use of additional hardware resources. The authorization key may be used akin to an insurance policy that allows selective increases in performance level to accommodate unplanned increases in performance requirements.