Patents by Inventor Kerry M. Pierce

Kerry M. Pierce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8099564
    Abstract: A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: January 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Chidamber R. Kulkarni, Schulyer E. Shimanek, Kerry M. Pierce, James A. Walstrum, Jr.
  • Patent number: 7992020
    Abstract: Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: August 2, 2011
    Assignee: Xilinx, Inc.
    Inventors: Tim Tuan, Kerry M. Pierce, Albert Franceschino
  • Patent number: 5801546
    Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: September 1, 1998
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Charles R. Erickson, Chih-Tsung Huang, Douglas P. Wieland
  • Patent number: 5760604
    Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: June 2, 1998
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Charles R. Erickson, Chih-Tsung Huang, Douglas P. Wieland
  • Patent number: 5646564
    Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: July 8, 1997
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Philip M. Freidin, Kerry M. Pierce
  • Patent number: 5581199
    Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: December 3, 1996
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Charles R. Erickson, Chih-Tsung Huang, Douglas P. Wieland
  • Patent number: 5489858
    Abstract: Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: February 6, 1996
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Charles R. Erickson
  • Patent number: 5481206
    Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: January 2, 1996
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, Kerry M. Pierce
  • Patent number: 5331220
    Abstract: Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: July 19, 1994
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Charles R. Erickson
  • Patent number: 5319252
    Abstract: The present invention reduces bounce in the power or ground supply voltages of an integrated circuit chip by gradually turning output drivers both on and off, so there is not a sharp discontinuity in current flow to an external device. Greatest current flow occurs at the middle of a transition period. The gradual turn-off at the end of a transition is achieved by feeding back voltage of the output signal to a device which controls the output driver. As output voltage approaches its final value, the output driver gradually turns off, preventing a sharp transient in the power or ground voltage of the integrated circuit chip.
    Type: Grant
    Filed: November 5, 1992
    Date of Patent: June 7, 1994
    Assignee: Xilinx, Inc.
    Inventors: Kerry M. Pierce, Roger D. Carpenter
  • Patent number: 5231311
    Abstract: A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: July 27, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas V. Ferry, Jamil Kawa, Kerry M. Pierce, William G. Walker, Michael A. Zampaglione, James S. Hsue
  • Patent number: 5179534
    Abstract: An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: January 12, 1993
    Assignee: CrossCheck Technology, Inc.
    Inventors: Kerry M. Pierce, Thomas V. Ferry
  • Patent number: 5146306
    Abstract: Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates.
    Type: Grant
    Filed: January 8, 1991
    Date of Patent: September 8, 1992
    Assignee: VLSI Technology, Inc
    Inventors: Thomas V. Ferry, Jamil Kawa, Kerry M. Pierce, William G. Walker, James S. Hsue
  • Patent number: 5111075
    Abstract: A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.
    Type: Grant
    Filed: March 5, 1991
    Date of Patent: May 5, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Thomas V. Ferry, Jamil Kawa, Kerry M. Pierce, William G. Walker, Michael A. Zampaglione