Patents by Inventor Kerry Nagel

Kerry Nagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12022738
    Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 25, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Sarin Deshpande, Kerry Nagel, Santosh Karre
  • Patent number: 11925122
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20220336734
    Abstract: A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.
    Type: Application
    Filed: April 14, 2022
    Publication date: October 20, 2022
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Santosh KARRE
  • Patent number: 11264564
    Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: March 1, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Hamid Almasi, Shimon, Kerry Nagel, Han Kyu Lee
  • Publication number: 20210408371
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason JANESKY
  • Publication number: 20210328138
    Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.
    Type: Application
    Filed: August 22, 2019
    Publication date: October 21, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Sarin DESHPANDE, Kerry NAGEL, Santosh KARRE
  • Patent number: 11139429
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 5, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20210249589
    Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Hamid ALMASI, SHIMON, Kerry NAGEL, Han Kyu LEE
  • Patent number: 11005031
    Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 11, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Nagel, Sanjeev Aggarwal
  • Publication number: 20200185602
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason Janesky
  • Patent number: 10608172
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 31, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20200075843
    Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 5, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry NAGEL, Sanjeev AGGARWAL
  • Publication number: 20190157550
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason Janesky
  • Patent number: 10230046
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 12, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20180123032
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9893275
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: February 13, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20170148980
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Application
    Filed: January 2, 2017
    Publication date: May 25, 2017
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9548442
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Grant
    Filed: July 12, 2015
    Date of Patent: January 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20150318465
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Application
    Filed: July 12, 2015
    Publication date: November 5, 2015
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9093640
    Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 28, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky