Patents by Inventor Kerry Tedrow
Kerry Tedrow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10748613Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: GrantFiled: October 31, 2018Date of Patent: August 18, 2020Assignee: MIcron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Publication number: 20190066783Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: ApplicationFiled: October 31, 2018Publication date: February 28, 2019Applicant: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Patent number: 10147487Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: GrantFiled: October 23, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Publication number: 20180047446Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Applicant: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Patent number: 9799398Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: GrantFiled: April 11, 2016Date of Patent: October 24, 2017Assignee: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Patent number: 9564181Abstract: A memory device comprising a memory array comprising a plurality of memory cells, a plurality of bitlines and a plurality of wordlines for writing to the plurality of memory cells and a sense amplifier coupled to a first bitline of the plurality of bitlines, for reading the contents of a selected memory cell, the sense amplifier comprising a first cascode transistor pair coupled to a second cascode transistor pair, the first cascode transistor pair coupled to the first bitline and a second bitline, and a current comparator coupled to a drain side of the second cascode transistor pair for determining a value of the selected memory cell.Type: GrantFiled: February 28, 2014Date of Patent: February 7, 2017Assignee: Sony Semiconductor Solutions CorporationInventor: Kerry Tedrow
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Publication number: 20160225444Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: ApplicationFiled: April 11, 2016Publication date: August 4, 2016Applicant: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Patent number: 9311999Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: GrantFiled: September 5, 2014Date of Patent: April 12, 2016Assignee: Micron Technology, Inc.Inventors: Makoto Kitagawa, Kerry Tedrow
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Publication number: 20150071011Abstract: A memory device comprising a memory array comprising a plurality of memory cells, a plurality of bitlines and a plurality of wordlines for writing to the plurality of memory cells and a sense amplifier coupled to a first bitline of the plurality of bitlines, for reading the contents of a selected memory cell, the sense amplifier comprising a first cascode transistor pair coupled to a second cascode transistor pair, the first cascode transistor pair coupled to the first bitline and a second bitline, and a current comparator coupled to a drain side of the second cascode transistor pair for determining a value of the selected memory cell.Type: ApplicationFiled: February 28, 2014Publication date: March 12, 2015Applicant: Sony CorporationInventor: Kerry Tedrow
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Publication number: 20150070972Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.Type: ApplicationFiled: September 5, 2014Publication date: March 12, 2015Inventors: Makoto Kitagawa, Kerry Tedrow
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Publication number: 20070268758Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: ApplicationFiled: August 7, 2007Publication date: November 22, 2007Applicant: INTEL CORPORATIONInventors: Ahsanur Rahman, Rezaul Haque, Kerry Tedrow
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Publication number: 20070171708Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.Type: ApplicationFiled: December 28, 2005Publication date: July 26, 2007Inventors: Kerry Tedrow, Dung Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad Monasa, Matthew Goldman
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Publication number: 20070002613Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: INTEL CORPORATIONInventors: Ahsanur Rahman, Rezaul Haque, Kerry Tedrow
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Publication number: 20060156097Abstract: A non-volatile memory may include at least one cell that functions as an analog counter. In one embodiment, the counter may count the number of cycles experienced by the memory and provide an indication when a predetermined number of cycles have been completed. The completion of the given number of cycles may indicate a reliability issue.Type: ApplicationFiled: November 30, 2004Publication date: July 13, 2006Inventors: Christian Camarce, Gerald Barkley, Hernan Castro, Kerry Tedrow
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Publication number: 20060132114Abstract: A step voltage generator includes multiple trimmable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.Type: ApplicationFiled: December 21, 2004Publication date: June 22, 2006Inventors: Hari Giduturi, Kerry Tedrow
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Publication number: 20060114054Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.Type: ApplicationFiled: November 30, 2004Publication date: June 1, 2006Inventors: Hari Giduturi, Kerry Tedrow
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Publication number: 20050285631Abstract: A latch includes a switch to equalize voltages of two complementary nodes. The latch also includes at least one transistor to decouple the latch from a power supply node.Type: ApplicationFiled: June 28, 2004Publication date: December 29, 2005Inventors: Matthew Goldman, Saad Monasa, Kerry Tedrow
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Publication number: 20050105338Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.Type: ApplicationFiled: November 13, 2003Publication date: May 19, 2005Inventors: Rajesh Sundaram, Jahanshir Javanifard, Kerry Tedrow, Priya Walimbe, Tom Ly, Raymond Zeng
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Publication number: 20030208699Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.Type: ApplicationFiled: May 23, 2003Publication date: November 6, 2003Inventors: Mase Taub, Rajesh Sundaram, Kerry Tedrow
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Patent number: 6628108Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.Type: GrantFiled: December 22, 2000Date of Patent: September 30, 2003Assignee: Intel CorporationInventors: Mase Taub, Rajesh Sundaram, Kerry Tedrow