Patents by Inventor Kerry Veenstra
Kerry Veenstra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090282306Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.Type: ApplicationFiled: July 15, 2009Publication date: November 12, 2009Applicant: Altera CorporationInventors: Ninh D. Ngo, Andy L. Lee, Kerry Veenstra
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Apparatus and method for low power routing of signals in a low voltage differential signaling system
Patent number: 7593499Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: August 4, 2005Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby -
Patent number: 7584456Abstract: A programmable logic device (PLD) is provided. The PLD includes a microprocessing unit (MPU) and a memory region functioning in a read only state. A Joint Test Action Group (JTAG) debug module in communication with the memory region is included in the PLD. The JTAG debug module is able to detect a breakpoint causing an interruption of a processing sequence executed by the MPU. Write control circuitry capable of issuing a signal enabling the memory region to transition from the read only state disallowing writes to a second state accepting write data from the MPU is included in the JTAG debug circuitry. In one embodiment, the write control circuitry issues the signal in response to a breakpoint induced either through hardware or software. A method of debugging a PLD is also provided.Type: GrantFiled: January 14, 2005Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Kerry Veenstra, Tim Allen
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Patent number: 7577055Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.Type: GrantFiled: October 31, 2007Date of Patent: August 18, 2009Assignee: Altera CorporationInventors: Ninh D. Ngo, Andy L. Lee, Kerry Veenstra
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Patent number: 7574533Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: February 27, 2008Date of Patent: August 11, 2009Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7512849Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: December 5, 2005Date of Patent: March 31, 2009Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Publication number: 20080157813Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: February 27, 2008Publication date: July 3, 2008Applicant: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7395360Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.Type: GrantFiled: September 21, 2005Date of Patent: July 1, 2008Assignee: Altera CorporationInventors: Jeffrey Orion Pritchard, Kerry Veenstra, Aaron Ferrucci, Paul Metzgen
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Publication number: 20080143378Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: February 27, 2008Publication date: June 19, 2008Applicant: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7356620Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: GrantFiled: June 10, 2003Date of Patent: April 8, 2008Assignee: Altera CorporationInventors: Renxin Xia, Juju Chacko Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Publication number: 20080052569Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: ALTERA CORPORATIONInventors: Ninh Ngo, Andy Lee, Kerry Veenstra
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Patent number: 7310757Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.Type: GrantFiled: October 10, 2002Date of Patent: December 18, 2007Assignee: Altera CorporationInventors: Ninh D. Ngo, Andy L. Lee, Kerry Veenstra
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Patent number: 7148722Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.Type: GrantFiled: October 10, 2003Date of Patent: December 12, 2006Assignee: Altera CorporationInventors: Richard G Cliff, Francis B Heile, Joseph Huang, David W Mendel, Bruce B Pedersen, Chiakang Sung, Kerry Veenstra, Bonnie I Wang
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Publication number: 20060038586Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.Type: ApplicationFiled: June 10, 2003Publication date: February 23, 2006Inventors: Renxin Xia, Juju Joyce, Nitin Prasad, Kerry Veenstra, Keith Duwel
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Patent number: 7000161Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.Type: GrantFiled: October 11, 2002Date of Patent: February 14, 2006Assignee: Altera CorporationInventors: Tim Allen, Michael Fairman, Mario Guzman, Bryan Hoyer, Chris Lane, Kerry Veenstra, Keith Duwel, Andy L. Lee
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Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system
Patent number: 6956920Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: March 21, 2000Date of Patent: October 18, 2005Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby -
Patent number: 6815981Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: GrantFiled: February 6, 2003Date of Patent: November 9, 2004Assignee: Altera CorporationInventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
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Patent number: 6759870Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: February 20, 2003Date of Patent: July 6, 2004Assignee: Altera CorporationInventors: Richard G. Cliff, Bahram Ahanin, Craig Schilling Lytle, Francis B. Heile, Bruce B. Pedersen, Kerry Veenstra
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Patent number: 6704889Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.Type: GrantFiled: August 6, 2002Date of Patent: March 9, 2004Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Alan L. Herrmann
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Patent number: 6646467Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.Type: GrantFiled: May 17, 2002Date of Patent: November 11, 2003Assignee: Altera CorporationInventors: Richard G. Cliff, Francis B. Heile, Joseph Huang, David W. Mendel, Bruce B. Pendersen, Chiakang Sung, Kerry Veenstra, Bonnie I. Wang