Patents by Inventor Kersi H. Vakil
Kersi H. Vakil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8559530Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: October 26, 2007Date of Patent: October 15, 2013Assignee: Intel CorporationInventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 8149928Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: May 18, 2010Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G. Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 8098783Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: GrantFiled: April 28, 2008Date of Patent: January 17, 2012Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
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Publication number: 20100226419Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Inventors: Jed D. Griffin, Jerry G. Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7720159Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: October 26, 2007Date of Patent: May 18, 2010Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7656983Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: GrantFiled: September 29, 2006Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7466723Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.Type: GrantFiled: June 29, 2004Date of Patent: December 16, 2008Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar
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Publication number: 20080260082Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: ApplicationFiled: April 28, 2008Publication date: October 23, 2008Inventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
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Publication number: 20080130815Abstract: Embodiments to selectively track serial communication link data are presented herein.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: S. Reji Kumar, Arnaud Forestier, Adarsh Panikkar, Kersi H. Vakil
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Publication number: 20080123722Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: ApplicationFiled: October 26, 2007Publication date: May 29, 2008Inventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7369634Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: GrantFiled: September 7, 2004Date of Patent: May 6, 2008Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
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Publication number: 20080080654Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7308025Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: July 23, 2003Date of Patent: December 11, 2007Assignee: Intel CorporationInventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7305023Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: July 23, 2003Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7050507Abstract: A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.Type: GrantFiled: April 22, 2002Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Kersi H. Vakil, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla
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Patent number: 7043392Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.Type: GrantFiled: June 16, 2004Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar, Abhimanyu Kolla, Arnaud Forestier
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Patent number: 7019550Abstract: A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.Type: GrantFiled: June 29, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Eric R. Wehage, Anne Meixner, Kersi H. Vakil
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Patent number: 7009431Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.Type: GrantFiled: June 29, 2004Date of Patent: March 7, 2006Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla, Arnaud Forestier
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Publication number: 20030200364Abstract: A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.Type: ApplicationFiled: April 22, 2002Publication date: October 23, 2003Applicant: Intel CorporationInventors: Kersi H. Vakil, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla
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Patent number: 6466074Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.Type: GrantFiled: March 30, 2001Date of Patent: October 15, 2002Assignee: Intel CorporationInventors: Kersi H. Vakil, William N. Roy, Jerry G. Jex