Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an input/output agent having multiple secondary ports. In some embodiments, the input/output agent includes a primary port to communicate data with an upstream agent over a serial point-to-point interconnect. The input/output agent may also include M secondary ports to communicate data with a corresponding M downstream agents, wherein downstream data is forwarded from the primary port to at least one of the M secondary ports.

Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.

Abstract: A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.

Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.

Abstract: A method to calibrate an equalizer for communicating signals over a data link between a transmitter and receiver includes measuring loss in the link and automatically determining a multi-tap equalization setting for the transmitter based on the measured loss. The multi-tap equalization setting may be determined using a look-up table, which stores a plurality of equalization settings for a respective number of link loss values. Once the equalization setting matching the measured link loss is found in the table, the equalizer can be optimally set to reduce or eliminate intersymbol and other types of interference.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.

Abstract: In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.

Abstract: Point-to-point AC impedance compensation calculates and matches AC impedance for integrated circuit input and output buffers, taking into consideration impedances of printed circuit boards, connectors, cards, cables, and/or other interfaces on a computer bus, upon computer system power-up or on demand during operation using no additional package pins or traces in the printed circuit board, connector, card, or cable.